arm64: dts: imx8mq-librem5-r3: workaround i2c1 issue with 1GHz cpu voltage

This is a workaround for a hardware bug in the r3 revision that basically would
stop the system due to traffic on the i2c1 bus. A cpu voltage change would
trigger such traffic and that's what is avoided in order to work around it.

Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
index 6704ea2c72a3556e144f5e2e546035d840d22383..0d38327043f880aa71dc495e447cc23cb34fe0fc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
@@ -10,6 +10,12 @@
        compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
 };
 
+&a53_opp_table {
+       opp-1000000000 {
+               opp-microvolt = <1000000>;
+       };
+};
+
 &accel_gyro {
        mount-matrix =  "1",  "0",  "0",
                        "0",  "1",  "0",