drm/i915/display: Store hw clock for C20

We can calculate the hw port clock during the hw readout
and store it as pll_state->clock for C20 state verification.
In order to do that we need to move intel_c20pll_calc_port_clock()
function.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-3-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6b25e195232f13376f9b435f04fa48c50c01abdd..fc7211675b2f55ea4364a2a7bef1f7379d6076a4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2105,6 +2105,51 @@ static bool intel_c20_use_mplla(u32 clock)
        return false;
 }
 
+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+                                       const struct intel_c20pll_state *pll_state)
+{
+       unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+       unsigned int multiplier, refclk = 38400;
+       unsigned int tx_clk_div;
+       unsigned int ref_clk_mpllb_div;
+       unsigned int fb_clk_div4_en;
+       unsigned int ref, vco;
+       unsigned int tx_rate_mult;
+       unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+       if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
+               tx_rate_mult = 1;
+               frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+               frac_quot = pll_state->mpllb[8];
+               frac_rem =  pll_state->mpllb[9];
+               frac_den =  pll_state->mpllb[7];
+               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+               tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
+               fb_clk_div4_en = 0;
+       } else {
+               tx_rate_mult = 2;
+               frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+               frac_quot = pll_state->mplla[8];
+               frac_rem =  pll_state->mplla[9];
+               frac_den =  pll_state->mplla[7];
+               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+               tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
+               fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
+       }
+
+       if (frac_en)
+               frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+       else
+               frac = 0;
+
+       ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
+       vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
+
+       return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
                                          struct intel_c20pll_state *pll_state)
 {
@@ -2160,6 +2205,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
                }
        }
 
+       pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
+
        intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
@@ -2408,51 +2455,6 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
        return tmpclk;
 }
 
-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-                                       const struct intel_c20pll_state *pll_state)
-{
-       unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
-       unsigned int multiplier, refclk = 38400;
-       unsigned int tx_clk_div;
-       unsigned int ref_clk_mpllb_div;
-       unsigned int fb_clk_div4_en;
-       unsigned int ref, vco;
-       unsigned int tx_rate_mult;
-       unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
-
-       if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
-               tx_rate_mult = 1;
-               frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
-               frac_quot = pll_state->mpllb[8];
-               frac_rem =  pll_state->mpllb[9];
-               frac_den =  pll_state->mpllb[7];
-               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
-               tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
-               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
-               fb_clk_div4_en = 0;
-       } else {
-               tx_rate_mult = 2;
-               frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
-               frac_quot = pll_state->mplla[8];
-               frac_rem =  pll_state->mplla[9];
-               frac_den =  pll_state->mplla[7];
-               multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
-               tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
-               ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
-               fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
-       }
-
-       if (frac_en)
-               frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
-       else
-               frac = 0;
-
-       ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
-       vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
-
-       return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
-}
-
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
                                         const struct intel_crtc_state *crtc_state,
                                         bool lane_reversal)
@@ -3071,6 +3073,11 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
        bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;
        int i;
 
+       I915_STATE_WARN(i915, mpll_hw_state->clock != mpll_sw_state->clock,
+                       "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
+                       crtc->base.base.id, crtc->base.name,
+                       mpll_sw_state->clock, mpll_hw_state->clock);
+
        I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
                        "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
                        crtc->base.base.id, crtc->base.name,