arm64: dts: imx8: switch to new lpcg clock binding

switch to new lpcg clock binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 30f2089cfdc42b2b5b60ed32c8125d7659083527..ff0696d806542f52c51de8afa3b58964d8d4ffa6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -20,13 +20,8 @@ adma_subsys: bus@59000000 {
                clock-output-names = "dma_ipg_clk";
        };
 
-       /* LPCG clocks */
-       adma_lpcg: clock-controller@59000000 {
-               reg = <0x59000000 0x2000000>;
-               #clock-cells = <1>;
-       };
-
        dsp_lpcg: clock-controller@59580000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x59580000 0x10000>;
                #clock-cells = <1>;
                clocks = <&dma_ipg_clk>,
@@ -41,6 +36,7 @@ adma_subsys: bus@59000000 {
        };
 
        dsp_ram_lpcg: clock-controller@59590000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x59590000 0x10000>;
                #clock-cells = <1>;
                clocks = <&dma_ipg_clk>;
@@ -52,9 +48,9 @@ adma_subsys: bus@59000000 {
        adma_dsp: dsp@596e8000 {
                compatible = "fsl,imx8qxp-dsp";
                reg = <0x596e8000 0x88000>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
-                       <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
-                       <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+               clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
+                        <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
+                        <&dsp_lpcg IMX_LPCG_CLK_7>;
                clock-names = "ipg", "ocram", "core";
                power-domains = <&pd IMX_SC_R_MU_13A>,
                        <&pd IMX_SC_R_MU_13B>,
@@ -73,8 +69,8 @@ adma_subsys: bus@59000000 {
        adma_lpuart0: serial@5a060000 {
                reg = <0x5a060000 0x1000>;
                interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
-                        <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
+               clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
+                        <&uart0_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "baud";
                power-domains = <&pd IMX_SC_R_UART_0>;
                status = "disabled";
@@ -83,8 +79,8 @@ adma_subsys: bus@59000000 {
        adma_lpuart1: serial@5a070000 {
                reg = <0x5a070000 0x1000>;
                interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
-                        <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+               clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
+                        <&uart1_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "baud";
                power-domains = <&pd IMX_SC_R_UART_1>;
                status = "disabled";
@@ -93,8 +89,8 @@ adma_subsys: bus@59000000 {
        adma_lpuart2: serial@5a080000 {
                reg = <0x5a080000 0x1000>;
                interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
-                        <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+               clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
+                        <&uart2_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "baud";
                power-domains = <&pd IMX_SC_R_UART_2>;
                status = "disabled";
@@ -103,14 +99,15 @@ adma_subsys: bus@59000000 {
        adma_lpuart3: serial@5a090000 {
                reg = <0x5a090000 0x1000>;
                interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
-                        <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+               clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
+                        <&uart3_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "baud";
                power-domains = <&pd IMX_SC_R_UART_3>;
                status = "disabled";
        };
 
        uart0_lpcg: clock-controller@5a460000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5a460000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
@@ -122,6 +119,7 @@ adma_subsys: bus@59000000 {
        };
 
        uart1_lpcg: clock-controller@5a470000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5a470000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
@@ -133,6 +131,7 @@ adma_subsys: bus@59000000 {
        };
 
        uart2_lpcg: clock-controller@5a480000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5a480000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
@@ -144,6 +143,7 @@ adma_subsys: bus@59000000 {
        };
 
        uart3_lpcg: clock-controller@5a490000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5a490000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
@@ -157,7 +157,7 @@ adma_subsys: bus@59000000 {
        adma_i2c0: i2c@5a800000 {
                reg = <0x5a800000 0x4000>;
                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
+               clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
                clock-names = "per";
                assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
@@ -168,7 +168,7 @@ adma_subsys: bus@59000000 {
        adma_i2c1: i2c@5a810000 {
                reg = <0x5a810000 0x4000>;
                interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
+               clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
                clock-names = "per";
                assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
@@ -179,7 +179,7 @@ adma_subsys: bus@59000000 {
        adma_i2c2: i2c@5a820000 {
                reg = <0x5a820000 0x4000>;
                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
+               clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
                clock-names = "per";
                assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
@@ -190,7 +190,7 @@ adma_subsys: bus@59000000 {
        adma_i2c3: i2c@5a830000 {
                reg = <0x5a830000 0x4000>;
                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
+               clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
                clock-names = "per";
                assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
                assigned-clock-rates = <24000000>;
@@ -199,6 +199,7 @@ adma_subsys: bus@59000000 {
        };
 
        i2c0_lpcg: clock-controller@5ac00000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5ac00000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
@@ -210,6 +211,7 @@ adma_subsys: bus@59000000 {
        };
 
        i2c1_lpcg: clock-controller@5ac10000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5ac10000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
@@ -221,6 +223,7 @@ adma_subsys: bus@59000000 {
        };
 
        i2c2_lpcg: clock-controller@5ac20000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5ac20000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
@@ -232,6 +235,7 @@ adma_subsys: bus@59000000 {
        };
 
        i2c3_lpcg: clock-controller@5ac30000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5ac30000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e2fe3bc2bceaf05bba36cfeeb520c2d9d7270606..e1e81ca0ca698a0e579bc982aae1dfc4bfb37b60 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -37,10 +37,10 @@ conn_subsys: bus@5b000000 {
        usdhc1: mmc@5b010000 {
                interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b010000 0x10000>;
-               clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
-               clock-names = "ipg", "ahb", "per";
+               clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
+                        <&sdhc0_lpcg IMX_LPCG_CLK_5>,
+                        <&sdhc0_lpcg IMX_LPCG_CLK_0>;
+               clock-names = "ipg", "per", "ahb";
                power-domains = <&pd IMX_SC_R_SDHC_0>;
                status = "disabled";
        };
@@ -48,10 +48,10 @@ conn_subsys: bus@5b000000 {
        usdhc2: mmc@5b020000 {
                interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b020000 0x10000>;
-               clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
-               clock-names = "ipg", "ahb", "per";
+               clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
+                        <&sdhc1_lpcg IMX_LPCG_CLK_5>,
+                        <&sdhc1_lpcg IMX_LPCG_CLK_0>;
+               clock-names = "ipg", "per", "ahb";
                power-domains = <&pd IMX_SC_R_SDHC_1>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step= <2>;
@@ -61,10 +61,10 @@ conn_subsys: bus@5b000000 {
        usdhc3: mmc@5b030000 {
                interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b030000 0x10000>;
-               clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
-               clock-names = "ipg", "ahb", "per";
+               clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
+                        <&sdhc2_lpcg IMX_LPCG_CLK_5>,
+                        <&sdhc2_lpcg IMX_LPCG_CLK_0>;
+               clock-names = "ipg", "per", "ahb";
                power-domains = <&pd IMX_SC_R_SDHC_2>;
                status = "disabled";
        };
@@ -75,10 +75,10 @@ conn_subsys: bus@5b000000 {
                             <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
+               clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
+                        <&enet0_lpcg IMX_LPCG_CLK_2>,
+                        <&enet0_lpcg IMX_LPCG_CLK_1>,
+                        <&enet0_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                fsl,num-tx-queues=<3>;
                fsl,num-rx-queues=<3>;
@@ -92,10 +92,10 @@ conn_subsys: bus@5b000000 {
                                <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
-                        <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
+               clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
+                        <&enet1_lpcg IMX_LPCG_CLK_2>,
+                        <&enet1_lpcg IMX_LPCG_CLK_1>,
+                        <&enet1_lpcg IMX_LPCG_CLK_0>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                fsl,num-tx-queues=<3>;
                fsl,num-rx-queues=<3>;
@@ -104,12 +104,8 @@ conn_subsys: bus@5b000000 {
        };
 
        /* LPCG clocks */
-       conn_lpcg: clock-controller-legacy@5b200000 {
-               reg = <0x5b200000 0xb0000>;
-               #clock-cells = <1>;
-       };
-
        sdhc0_lpcg: clock-controller@5b200000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b200000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
@@ -123,6 +119,7 @@ conn_subsys: bus@5b000000 {
        };
 
        sdhc1_lpcg: clock-controller@5b210000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b210000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
@@ -136,6 +133,7 @@ conn_subsys: bus@5b000000 {
        };
 
        sdhc2_lpcg: clock-controller@5b220000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b220000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
@@ -149,6 +147,7 @@ conn_subsys: bus@5b000000 {
        };
 
        enet0_lpcg: clock-controller@5b230000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b230000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
@@ -166,6 +165,7 @@ conn_subsys: bus@5b000000 {
        };
 
        enet1_lpcg: clock-controller@5b240000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b240000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 813dbac71d101ee9c47236a534adc44e3b4377e2..ee4e585a9c391aff4358d555204258cd70c6e292 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -149,12 +149,8 @@ lsio_subsys: bus@5d000000 {
        };
 
        /* LPCG clocks */
-       lsio_lpcg: clock-controller-legacy@5d400000 {
-               reg = <0x5d400000 0x400000>;
-               #clock-cells = <1>;
-       };
-
        pwm0_lpcg: clock-controller@5d400000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d400000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
@@ -174,6 +170,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm1_lpcg: clock-controller@5d410000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d410000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
@@ -193,6 +190,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm2_lpcg: clock-controller@5d420000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d420000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
@@ -212,6 +210,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm3_lpcg: clock-controller@5d430000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d430000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
@@ -231,6 +230,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm4_lpcg: clock-controller@5d440000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d440000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
@@ -250,6 +250,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm5_lpcg: clock-controller@5d450000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d450000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
@@ -269,6 +270,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm6_lpcg: clock-controller@5d460000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d460000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
@@ -288,6 +290,7 @@ lsio_subsys: bus@5d000000 {
        };
 
        pwm7_lpcg: clock-controller@5d470000 {
+               compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5d470000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
index 64e51dda2dfd7750f00915b62308c52bac9a1184..3dc3238e7ca6855f05a089accaa334c366de0ef1 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -4,10 +4,6 @@
  *     Dong Aisheng <aisheng.dong@nxp.com>
  */
 
-&adma_lpcg {
-       compatible = "fsl,imx8qxp-lpcg-adma";
-};
-
 &adma_lpuart0 {
        compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
index bed3934ca02904f796d1d60b7b82ec01279f685d..f5f58959f65ceffe0877cce5425656431a07cf2b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
@@ -4,10 +4,6 @@
  *     Dong Aisheng <aisheng.dong@nxp.com>
  */
 
-&conn_lpcg {
-       compatible = "fsl,imx8qxp-lpcg-conn";
-};
-
 &usdhc1 {
        compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index 82cebf04fca94862180a25333095e1194d110128..11395479ffc0125ade09f436cf253a9222bbaa55 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -59,7 +59,3 @@
 &lsio_mu13 {
        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 };
-
-&lsio_lpcg {
-       compatible = "fsl,imx8qxp-lpcg-lsio";
-};

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 095d3f69a9b7d09f46fd98b1a548ab9f4f2b3692..9513bb7b5c894f92a3d718b43461300cd280826a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>