#ifdef CONFIG_ARM64
        /* ECV is likely to require a large divider. Use the EVNTIS flag. */
-       if (cpus_have_const_cap(ARM64_HAS_ECV) && divider > 15) {
+       if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
                cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
                divider -= 8;
        }
        arch_timer_evtstrm_enable(max(0, lsb));
 }
 
+static int arch_timer_evtstrm_starting_cpu(unsigned int cpu)
+{
+       arch_timer_configure_evtstream();
+       return 0;
+}
+
+static int arch_timer_evtstrm_dying_cpu(unsigned int cpu)
+{
+       cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
+       return 0;
+}
+
+static int __init arch_timer_evtstrm_register(void)
+{
+       if (!arch_timer_evt || !evtstrm_enable)
+               return 0;
+
+       return cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING,
+                                "clockevents/arm/arch_timer_evtstrm:starting",
+                                arch_timer_evtstrm_starting_cpu,
+                                arch_timer_evtstrm_dying_cpu);
+}
+core_initcall(arch_timer_evtstrm_register);
+
 static void arch_counter_set_user_access(void)
 {
        u32 cntkctl = arch_timer_get_cntkctl();
        }
 
        arch_counter_set_user_access();
-       if (evtstrm_enable)
-               arch_timer_configure_evtstream();
 
        return 0;
 }
 {
        struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
 
-       cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
-
        arch_timer_stop(clk);
        return 0;
 }
 
 out_free:
        free_percpu(arch_timer_evt);
+       arch_timer_evt = NULL;
 out:
        return err;
 }
 
        CPUHP_AP_ARM_L2X0_STARTING,
        CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
        CPUHP_AP_ARM_ARCH_TIMER_STARTING,
+       CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING,
        CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
        CPUHP_AP_JCORE_TIMER_STARTING,
        CPUHP_AP_ARM_TWD_STARTING,