drm/amd/display: Add DIG_CLOCK_PATTERN in the transmitter control

[Why and How]
VBIOS program DIG_CLK_PATTERN using engine ID instead of PHY ID.
Workaround by writing value for 0x1f (for HDMI) after calling vbios.

Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 81db0179f7ea8ac381b976c0ccbd28cbc36baa43..59024653430cd714f3a7e5346001028e383c6bcb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -956,6 +956,21 @@ void dcn10_link_encoder_enable_tmds_output(
        }
 }
 
+void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
+       struct link_encoder *enc,
+       enum clock_source_id clock_source,
+       enum dc_color_depth color_depth,
+       enum signal_type signal,
+       uint32_t pixel_clock)
+{
+       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+       dcn10_link_encoder_enable_tmds_output(
+               enc, clock_source, color_depth, signal, pixel_clock);
+
+       REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
+}
+
 /* enables DP PHY output */
 void dcn10_link_encoder_enable_dp_output(
        struct link_encoder *enc,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index d4caad67085547eafb75d9b4e7d90691fd57dccd..3e1a582e4b88fd58708ad663fde21159ea8e4200 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -42,6 +42,7 @@
 #define LE_DCN_COMMON_REG_LIST(id) \
        SRI(DIG_BE_CNTL, DIG, id), \
        SRI(DIG_BE_EN_CNTL, DIG, id), \
+       SRI(DIG_CLOCK_PATTERN, DIG, id), \
        SRI(TMDS_CTL_BITS, DIG, id), \
        SRI(DP_CONFIG, DP, id), \
        SRI(DP_DPHY_CNTL, DP, id), \
@@ -83,6 +84,7 @@ struct dcn10_link_enc_hpd_registers {
 struct dcn10_link_enc_registers {
        uint32_t DIG_BE_CNTL;
        uint32_t DIG_BE_EN_CNTL;
+       uint32_t DIG_CLOCK_PATTERN;
        uint32_t DP_CONFIG;
        uint32_t DP_DPHY_CNTL;
        uint32_t DP_DPHY_INTERNAL_CTRL;
@@ -168,6 +170,7 @@ struct dcn10_link_enc_registers {
        LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
        LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
        LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
+       LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
        LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
        LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
@@ -218,6 +221,7 @@ struct dcn10_link_enc_registers {
        type DIG_HPD_SELECT;\
        type DIG_MODE;\
        type DIG_FE_SOURCE_SELECT;\
+       type DIG_CLOCK_PATTERN;\
        type DPHY_BYPASS;\
        type DPHY_ATEST_SEL_LANE0;\
        type DPHY_ATEST_SEL_LANE1;\
@@ -536,6 +540,13 @@ void dcn10_link_encoder_enable_tmds_output(
        enum signal_type signal,
        uint32_t pixel_clock);
 
+void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
+       struct link_encoder *enc,
+       enum clock_source_id clock_source,
+       enum dc_color_depth color_depth,
+       enum signal_type signal,
+       uint32_t pixel_clock);
+
 /* enables DP PHY output */
 void dcn10_link_encoder_enable_dp_output(
        struct link_encoder *enc,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index 15c2ff264ff601f559a9fba0eabcf15ae68f9c36..fa013496e26baf8ae1aa817d6c9fcf389633420b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -363,7 +363,7 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = {
                dcn10_link_encoder_validate_output_with_stream,
        .hw_init = enc2_hw_init,
        .setup = dcn10_link_encoder_setup,
-       .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+       .enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa,
        .enable_dp_output = dcn20_link_encoder_enable_dp_output,
        .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
        .disable_output = dcn10_link_encoder_disable_output,