octeontx2-af: avoid RXC register access for CN10KB

This patch modifies the driver to prevent access to RXC hardware
registers on the CN10KB, as RXC is not available on this chip.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 03ee93fd9e9498f02daa9b64b4dab364f8337493..64c9c9ee000d65408055243c045f9fd8e4e3c1c6 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -400,6 +400,7 @@ struct hw_cap {
        bool    nix_multiple_dwrr_mtu;   /* Multiple DWRR_MTU to choose from */
        bool    npc_hash_extract; /* Hash extract enabled ? */
        bool    npc_exact_match_enabled; /* Exact match supported ? */
+       bool    cpt_rxc;   /* Is CPT-RXC supported */
 };
 
 struct rvu_hwinfo {
@@ -690,6 +691,15 @@ static inline bool is_cnf10ka_a0(struct rvu *rvu)
        return false;
 }
 
+static inline bool is_cn10kb(struct rvu *rvu)
+{
+       struct pci_dev *pdev = rvu->pdev;
+
+       if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B)
+               return true;
+       return false;
+}
+
 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
 {
        u64 npc_const3;

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index cd5b21cb04271ada9c92ec451bd0f35546136807..d44614a63a7bba934c26de7633946ed50764f1f8 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -789,6 +789,8 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
 
 static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
 {
+       struct rvu_hwinfo *hw = rvu->hw;
+
        if (is_rvu_otx2(rvu))
                return;
 
@@ -812,14 +814,16 @@ static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
        rsp->ctx_err = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ERR);
        rsp->ctx_enc_id = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ENC_ID);
        rsp->ctx_flush_timer = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FLUSH_TIMER);
+       rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0));
+       rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1));
 
+       if (!hw->cap.cpt_rxc)
+               return;
        rsp->rxc_time = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME);
        rsp->rxc_time_cfg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG);
        rsp->rxc_active_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);
        rsp->rxc_zombie_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);
        rsp->rxc_dfrg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG);
-       rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0));
-       rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1));
 }
 
 static void get_eng_sts(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
@@ -1004,10 +1008,11 @@ int rvu_mbox_handler_cpt_flt_eng_info(struct rvu *rvu, struct cpt_flt_eng_info_r
 static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)
 {
        struct cpt_rxc_time_cfg_req req, prev;
+       struct rvu_hwinfo *hw = rvu->hw;
        int timeout = 2000;
        u64 reg;
 
-       if (is_rvu_otx2(rvu))
+       if (!hw->cap.cpt_rxc)
                return;
 
        /* Set time limit to minimum values, so that rxc entries will be
@@ -1282,8 +1287,14 @@ unlock:
 
 int rvu_cpt_init(struct rvu *rvu)
 {
+       struct rvu_hwinfo *hw = rvu->hw;
+
        /* Retrieve CPT PF number */
        rvu->cpt_pf_num = get_cpt_pf_num(rvu);
+       if (is_block_implemented(rvu->hw, BLKADDR_CPT0) && !is_rvu_otx2(rvu) &&
+           !is_cn10kb(rvu))
+               hw->cap.cpt_rxc = true;
+
        spin_lock_init(&rvu->cpt_intr_lock);
 
        return 0;