arm64: dts: rockchip: Add thermal nodes to RK3576

Add the TSADC node to the RK3576. Additionally, add everything the TSADC
needs to function, i.e. thermal zones, their trip points and maps, as
well as adjust the CPU cooling-cells property.

The polling-delay properties are set to 0 as we do have interrupts for
this TSADC on this particular SoC, though the polling-delay-passive
properties are set to 100 for the thermal zones that have a passive
cooling device, as otherwise the thermal throttling behaviour never
unthrottles.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index c3cdae8a54941a75821aa6a642c535ced66a116a..2ec752b12b41d8d7af1ffcbe522dc9cfad75a320 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/power/rockchip,rk3576-power.h>
 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
        compatible = "rockchip,rk3576";
@@ -113,9 +114,9 @@
                        capacity-dmips-mhz = <485>;
                        clocks = <&scmi_clk SCMI_ARMCLK_L>;
                        operating-points-v2 = <&cluster0_opp_table>;
-                       #cooling-cells = <2>;
                        dynamic-power-coefficient = <120>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_l1: cpu@1 {
@@ -127,6 +128,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_L>;
                        operating-points-v2 = <&cluster0_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_l2: cpu@2 {
@@ -138,6 +140,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_L>;
                        operating-points-v2 = <&cluster0_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_l3: cpu@3 {
@@ -149,6 +152,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_L>;
                        operating-points-v2 = <&cluster0_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_b0: cpu@100 {
@@ -159,9 +163,9 @@
                        capacity-dmips-mhz = <1024>;
                        clocks = <&scmi_clk SCMI_ARMCLK_B>;
                        operating-points-v2 = <&cluster1_opp_table>;
-                       #cooling-cells = <2>;
                        dynamic-power-coefficient = <320>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_b1: cpu@101 {
@@ -173,6 +177,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_B>;
                        operating-points-v2 = <&cluster1_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_b2: cpu@102 {
@@ -184,6 +189,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_B>;
                        operating-points-v2 = <&cluster1_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                cpu_b3: cpu@103 {
@@ -195,6 +201,7 @@
                        clocks = <&scmi_clk SCMI_ARMCLK_B>;
                        operating-points-v2 = <&cluster1_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       #cooling-cells = <2>;
                };
 
                idle-states {
@@ -520,6 +527,143 @@
                method = "smc";
        };
 
+       thermal_zones: thermal-zones {
+               /* sensor near the center of the SoC */
+               package_thermal: package-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 0>;
+
+                       trips {
+                               package_crit: package-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               /* sensor for cluster1 (big Cortex-A72 cores) */
+               bigcore_thermal: bigcore-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 1>;
+
+                       trips {
+                               bigcore_alert: bigcore-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               bigcore_crit: bigcore-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&bigcore_alert>;
+                                       cooling-device =
+                                               <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               /* sensor for cluster0 (little Cortex-A53 cores) */
+               littlecore_thermal: littlecore-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 2>;
+
+                       trips {
+                               littlecore_alert: littlecore-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               littlecore_crit: littlecore-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&littlecore_alert>;
+                                       cooling-device =
+                                               <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                               <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               gpu_thermal: gpu-thermal {
+                       polling-delay-passive = <100>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 3>;
+
+                       trips {
+                               gpu_alert: gpu-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               gpu_crit: gpu-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&gpu_alert>;
+                                       cooling-device =
+                                               <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               npu_thermal: npu-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 4>;
+
+                       trips {
+                               npu_crit: npu-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+
+               ddr_thermal: ddr-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&tsadc 5>;
+
+                       trips {
+                               ddr_crit: ddr-crit {
+                                       temperature = <115000>;
+                                       hysteresis = <0>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
@@ -2303,6 +2447,22 @@
                        status = "disabled";
                };
 
+               tsadc: tsadc@2ae70000 {
+                       compatible = "rockchip,rk3576-tsadc";
+                       reg = <0x0 0x2ae70000 0x0 0x400>;
+                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+                       clock-names = "tsadc", "apb_pclk";
+                       assigned-clocks = <&cru CLK_TSADC>;
+                       assigned-clock-rates = <2000000>;
+                       resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
+                       reset-names = "tsadc-apb", "tsadc";
+                       #thermal-sensor-cells = <1>;
+                       rockchip,hw-tshut-temp = <120000>;
+                       rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+                       rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+               };
+
                i2c9: i2c@2ae80000 {
                        compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
                        reg = <0x0 0x2ae80000 0x0 0x1000>;