mask |= BIT(intel_display_port_power_domain(intel_encoder));
        }
 
+       if (crtc_state->shared_dpll)
+               mask |= BIT(POWER_DOMAIN_PLLS);
+
        return mask;
 }
 
 
                DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
                              pll->name, pll->config.crtc_mask, pll->on);
-
-               if (pll->config.crtc_mask)
-                       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
        }
 
        for_each_intel_encoder(dev, encoder) {
 
        }
        WARN_ON(pll->on);
 
-       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
-
        DRM_DEBUG_KMS("enabling %s\n", pll->name);
        pll->funcs.enable(dev_priv, pll);
        pll->on = true;
        DRM_DEBUG_KMS("disabling %s\n", pll->name);
        pll->funcs.disable(dev_priv, pll);
        pll->on = false;
-
-       intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
 static struct intel_shared_dpll *