};
 #endif
 
+/* 671b10b5-42c0-4696-9227-eb28d1b049d6 */
+static const u8 simult_central_periph_uuid[16] = {
+       0xd6, 0x49, 0xb0, 0xd1, 0x28, 0xeb, 0x27, 0x92,
+       0x96, 0x46, 0xc0, 0x42, 0xb5, 0x10, 0x1b, 0x67,
+};
+
 static int read_exp_features_info(struct sock *sk, struct hci_dev *hdev,
                                  void *data, u16 data_len)
 {
-       char buf[42];
+       char buf[44];
        struct mgmt_rp_read_exp_features_info *rp = (void *)buf;
        u16 idx = 0;
+       u32 flags;
 
        bt_dev_dbg(hdev, "sock %p", sk);
 
 
 #ifdef CONFIG_BT_FEATURE_DEBUG
        if (!hdev) {
-               u32 flags = bt_dbg_get() ? BIT(0) : 0;
+               flags = bt_dbg_get() ? BIT(0) : 0;
 
                memcpy(rp->features[idx].uuid, debug_uuid, 16);
                rp->features[idx].flags = cpu_to_le32(flags);
        }
 #endif
 
+       if (hdev) {
+               if (test_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks) &&
+                   (hdev->le_states[4] & 0x08) &&      /* Central */
+                   (hdev->le_states[4] & 0x40) &&      /* Peripheral */
+                   (hdev->le_states[3] & 0x10))        /* Simultaneous */
+                       flags = BIT(0);
+               else
+                       flags = 0;
+
+               memcpy(rp->features[idx].uuid, simult_central_periph_uuid, 16);
+               rp->features[idx].flags = cpu_to_le32(flags);
+               idx++;
+       }
+
        rp->feature_count = cpu_to_le16(idx);
 
        /* After reading the experimental features information, enable