* Patch by Stefan Roese, 13 Jun 2002:

  - PPC405GPr support completed: To support this and all other 16kB
    DCache 405 ppc's, make sure to set CFG_DCACHE_SIZE to 16kB in
    your config file (see config_CPCI4052.h, doesn't hurt on 8kB
    ppc's).

* Patch by Thomas Viehweger, 13 Jun 2002:
  Fix CPM reset on MPC8xx systems

diff --git a/CHANGELOG b/CHANGELOG
index 6cb222b8aa760af478ac3b26f715b1e1e5d0d332..6cb90ec541188ba2089425932c8d2d4936470ed0 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -14,6 +14,15 @@
 Modifications for 1.1.6:
 ======================================================================
 
+* Patch by Stefan Roese, 13 Jun 2002:
+  - PPC405GPr support completed: To support this and all other 16kB
+    DCache 405 ppc's, make sure to set CFG_DCACHE_SIZE to 16kB in
+    your config file (see config_CPCI4052.h, doesn't hurt on 8kB
+    ppc's).
+
+* Patch by Thomas Viehweger, 13 Jun 2002:
+  Fix CPM reset on MPC8xx systems
+
 * Add support for Siemens SCM board;
   update CCM board configuration; use common code where possible.
 

diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index 52c7f860619bdbf57c96d9017a98b1ba7d0c6eb1..298ff01a48f468192a3bf54e0c4588e4629aec57 100644 (file)
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -206,7 +206,7 @@ cpu_init_f (volatile immap_t *immr)
     /*
      * Reset CPM
      */
-    immr->im_cpm.cp_cpcr = CPM_CR_RST;
+    immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
     do {                               /* Spin until command processed         */
        __asm__ ("eieio");
     } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a368c476cd7d221af92e46a3f15e0aa78d45e172..f018242274b0a32380dcf97f7889b2ceca2eff73 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -112,16 +112,13 @@ int checkcpu(long clock)
                printf("external PCI arbiter enabled\n");
 #endif
 
-       switch (pvr) {
-       case PVR_405GP_RB:
-       case PVR_405GP_RC:
-       case PVR_405GP_RD:
-       case PVR_405CR_RA:
-       case PVR_405CR_RB:
+       if ((pvr | 0x00000001) == PVR_405GPR_RA) {
+               printf("           16 kB I-Cache 16 kB D-Cache");
+       } else {
                printf("           16 kB I-Cache 8 kB D-Cache");
-               break;
        }
 
+
 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 
 #ifdef CONFIG_IOP480

diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 6071a09b166c99fe962424f9b854014e0d44c258..ced1fa427852ac32226845fe5b247f1823ad4b7e 100644 (file)
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -38,154 +38,137 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
 {
        unsigned long pllmr;
        unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
+       uint pvr = get_pvr();
+       unsigned long psr;
+       unsigned long m;
 
        /*
         * Read PLL Mode register
         */
        pllmr = mfdcr (pllmd);
 
+       /*
+        * Read Pin Strapping register
+        */
+       psr = mfdcr (strap);
+
        /*
         * Determine FWD_DIV.
         */
-       switch (pllmr & PLLMR_FWD_DIV_MASK) {
-       case PLLMR_FWD_DIV_BYPASS:
-               sysInfo->pllFwdDiv = 1;
-               break;
-       case PLLMR_FWD_DIV_3:
-               sysInfo->pllFwdDiv = 3;
-               break;
-       case PLLMR_FWD_DIV_4:
-               sysInfo->pllFwdDiv = 4;
-               break;
-       case PLLMR_FWD_DIV_6:
-               sysInfo->pllFwdDiv = 6;
-               break;
-       default:
-               printf ("\nInvalid FWDDIV bits in PLL Mode reg: %8.8lx\a\n",
-                       pllmr);
-               hang ();
-       }
+       sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
 
        /*
         * Determine FBK_DIV.
         */
-       switch (pllmr & PLLMR_FB_DIV_MASK) {
-       case PLLMR_FB_DIV_1:
-               sysInfo->pllFbkDiv = 1;
-               break;
-       case PLLMR_FB_DIV_2:
-               sysInfo->pllFbkDiv = 2;
-               break;
-       case PLLMR_FB_DIV_3:
-               sysInfo->pllFbkDiv = 3;
-               break;
-       case PLLMR_FB_DIV_4:
-               sysInfo->pllFbkDiv = 4;
-               break;
+       sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
+       if (sysInfo->pllFbkDiv == 0) {
+               sysInfo->pllFbkDiv = 16;
        }
 
        /*
         * Determine PLB_DIV.
         */
-       switch (pllmr & PLLMR_CPU_TO_PLB_MASK) {
-       case PLLMR_CPU_PLB_DIV_1:
-               sysInfo->pllPlbDiv = 1;
-               break;
-       case PLLMR_CPU_PLB_DIV_2:
-               sysInfo->pllPlbDiv = 2;
-               break;
-       case PLLMR_CPU_PLB_DIV_3:
-               sysInfo->pllPlbDiv = 3;
-               break;
-       case PLLMR_CPU_PLB_DIV_4:
-               sysInfo->pllPlbDiv = 4;
-               break;
-       }
+       sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
 
        /*
         * Determine PCI_DIV.
         */
-       switch (pllmr & PLLMR_PCI_TO_PLB_MASK) {
-       case PLLMR_PCI_PLB_DIV_1:
-               sysInfo->pllPciDiv = 1;
-               break;
-       case PLLMR_PCI_PLB_DIV_2:
-               sysInfo->pllPciDiv = 2;
-               break;
-       case PLLMR_PCI_PLB_DIV_3:
-               sysInfo->pllPciDiv = 3;
-               break;
-       case PLLMR_PCI_PLB_DIV_4:
-               sysInfo->pllPciDiv = 4;
-               break;
-       }
+       sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
 
        /*
         * Determine EXTBUS_DIV.
         */
-       switch (pllmr & PLLMR_EXB_TO_PLB_MASK) {
-       case PLLMR_EXB_PLB_DIV_2:
-               sysInfo->pllExtBusDiv = 2;
-               break;
-       case PLLMR_EXB_PLB_DIV_3:
-               sysInfo->pllExtBusDiv = 3;
-               break;
-       case PLLMR_EXB_PLB_DIV_4:
-               sysInfo->pllExtBusDiv = 4;
-               break;
-       case PLLMR_EXB_PLB_DIV_5:
-               sysInfo->pllExtBusDiv = 5;
-               break;
-       }
+       sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
 
        /*
         * Determine OPB_DIV.
         */
-       switch (pllmr & PLLMR_OPB_TO_PLB_MASK) {
-       case PLLMR_OPB_PLB_DIV_1:
-               sysInfo->pllOpbDiv = 1;
-               break;
-       case PLLMR_OPB_PLB_DIV_2:
-               sysInfo->pllOpbDiv = 2;
-               break;
-       case PLLMR_OPB_PLB_DIV_3:
-               sysInfo->pllOpbDiv = 3;
-               break;
-       case PLLMR_OPB_PLB_DIV_4:
-               sysInfo->pllOpbDiv = 4;
-               break;
-       }
+       sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
 
        /*
-        * Check pllFwdDiv to see if running in bypass mode where the CPU speed
-        * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
-        * to make sure it is within the proper range.
-        *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
-        * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
+        * Check if PPC405GPr used (mask minor revision field)
         */
-       if (sysInfo->pllFwdDiv == 1) {
-               sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
-               sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
+       if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) {
+               /*
+                * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
+                */
+               sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
+
+               /*
+                * Determine factor m depending on PLL feedback clock source
+                */
+               if (!(psr & PSR_PCI_ASYNC_EN)) {
+                       if (psr & PSR_NEW_MODE_EN) {
+                               /*
+                                * sync pci clock used as feedback (new mode)
+                                */
+                               m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
+                       } else {
+                               /*
+                                * sync pci clock used as feedback (legacy mode)
+                                */
+                               m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
+                       }
+               } else if (psr & PSR_NEW_MODE_EN) {
+                       if (psr & PSR_PERCLK_SYNC_MODE_EN) {
+                               /*
+                                * PerClk used as feedback (new mode)
+                                */
+                               m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
+                       } else {
+                               /*
+                                * CPU clock used as feedback (new mode)
+                                */
+                               m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
+                       }
+               } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
+                       /*
+                        * PerClk used as feedback (legacy mode)
+                        */
+                       m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
+               } else {
+                       /*
+                        * PLB clock used as feedback (legacy mode)
+                        */
+                       m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
+               }
+
+               sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
+               sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
+               sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
+                       (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
        } else {
-               sysInfo->freqVCOMhz = ( 1000000 *
-                                       sysInfo->pllFwdDiv *
-                                       sysInfo->pllFbkDiv *
-                                       sysInfo->pllPlbDiv
-                                     ) / sysClkPeriodPs;
-               if (sysInfo->freqVCOMhz >= VCO_MIN
-                       && sysInfo->freqVCOMhz <= VCO_MAX) {
-                       sysInfo->freqPLB = (ONE_BILLION /
-                                       ((sysClkPeriodPs * 10) /
-                                        sysInfo->pllFbkDiv)) * 10000;
-                       sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
+               /*
+                * Check pllFwdDiv to see if running in bypass mode where the CPU speed
+                * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
+                * to make sure it is within the proper range.
+                *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
+                * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
+                */
+               if (sysInfo->pllFwdDiv == 1) {
+                       sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
+                       sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
                } else {
-                       printf ("\nInvalid VCO frequency calculated :  %ld MHz \a\n",
-                               sysInfo->freqVCOMhz);
-                       printf ("It must be between %d-%d MHz \a\n",
-                               VCO_MIN, VCO_MAX);
-                       printf ("PLL Mode reg           :  %8.8lx\a\n",
-                               pllmr);
-                       hang ();
+                       sysInfo->freqVCOMhz = ( 1000000 *
+                                               sysInfo->pllFwdDiv *
+                                               sysInfo->pllFbkDiv *
+                                               sysInfo->pllPlbDiv
+                               ) / sysClkPeriodPs;
+                       if (sysInfo->freqVCOMhz >= VCO_MIN
+                           && sysInfo->freqVCOMhz <= VCO_MAX) {
+                               sysInfo->freqPLB = (ONE_BILLION /
+                                                   ((sysClkPeriodPs * 10) /
+                                                    sysInfo->pllFbkDiv)) * 10000;
+                               sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
+                       } else {
+                               printf ("\nInvalid VCO frequency calculated :  %ld MHz \a\n",
+                                       sysInfo->freqVCOMhz);
+                               printf ("It must be between %d-%d MHz \a\n",
+                                       VCO_MIN, VCO_MAX);
+                               printf ("PLL Mode reg           :  %8.8lx\a\n",
+                                       pllmr);
+                               hang ();
+                       }
                }
        }
 }

diff --git a/include/asm/processor.h b/include/asm/processor.h
index 4747a8f76bb4fcfd1439959410a23393bfdc7275..3a831d3131fa67ddef635e28ce052dd4ba3c4f9b 100644 (file)
--- a/include/asm/processor.h
+++ b/include/asm/processor.h
@@ -462,7 +462,7 @@
 #define        PVR_405CR_RA    0x40110041
 #define        PVR_405CR_RB    0x401100C5
 #define        PVR_405CR_RC    0x40110145  /* same as pc405gp rev e */
-#define        PVR_405GPR_RA   0x50910950
+#define        PVR_405GPR_RA   0x50910951
 #define        PVR_440GP_RC    0x40120400
 #define        PVR_601         0x00010000
 #define        PVR_602         0x00050000

diff --git a/include/config_CPCI4052.h b/include/config_CPCI4052.h
index e702d406cddf323d2b8658e8573758cf73ad946c..913ae4627e11b78c64774f382ec3d73d24987b6b 100644 (file)
--- a/include/config_CPCI4052.h
+++ b/include/config_CPCI4052.h
@@ -256,7 +256,8 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
+#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 1e5d6628c0c493037aba3726370c3e7ff9c0eca6..f6780dd3552014ebffd04256c12615811b031f5d 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -279,6 +279,9 @@
 #define PLLMR_EXB_PLB_DIV_4     0x00001000
 #define PLLMR_EXB_PLB_DIV_5     0x00001800
 
+/* definitions for PPC405GPr (new mode strapping) */
+#define PLLMR_FWDB_DIV_MASK     0x00000007     /* Forward Divisor B */
+
 #define PSR_PLL_FWD_MASK        0xC0000000
 #define PSR_PLL_FDBACK_MASK     0x30000000
 #define PSR_PLL_TUNING_MASK     0x0E000000
@@ -289,7 +292,9 @@
 #define PSR_ROM_WIDTH_MASK      0x00018000
 #define PSR_ROM_LOC             0x00004000
 #define PSR_PCI_ASYNC_EN        0x00001000
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
 #define PSR_PCI_ARBIT_EN        0x00000400
+#define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
 
 /*
  * PLL Voltage Controlled Oscillator (VCO) definitions
@@ -374,6 +379,7 @@
 typedef struct
 {
   unsigned long pllFwdDiv;
+  unsigned long pllFwdDivB;
   unsigned long pllFbkDiv;
   unsigned long pllPlbDiv;
   unsigned long pllPciDiv;