};
 
 struct device_node;
+struct irq_domain;
 struct irq_domain_ops;
+
 struct ioapic_domain_cfg {
        enum ioapic_domain_type         type;
        const struct irq_domain_ops     *ops;
 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags);
 extern void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
                                      struct ioapic_domain_cfg *cfg);
+extern int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
+                           irq_hw_number_t hwirq);
+extern int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node);
 extern void __init pre_init_apic_IRQ0(void);
 
 extern void mp_save_irq(struct mpc_intsrc *m);
 
 static DEFINE_MUTEX(ioapic_mutex);
 static unsigned int ioapic_dynirq_base;
 
+struct mp_pin_info {
+       int trigger;
+       int polarity;
+       int node;
+       int set;
+       u32 count;
+};
+
 static struct ioapic {
        /*
         * # of IRQ routing registers
        struct mp_ioapic_gsi  gsi_config;
        struct ioapic_domain_cfg irqdomain_cfg;
        struct irq_domain *irqdomain;
+       struct mp_pin_info *pin_info;
        DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
 } ioapics[MAX_IO_APICS];
 
        return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
 }
 
+static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
+{
+       return ioapics[ioapic_idx].pin_info + pin;
+}
+
 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
 {
        return ioapics[ioapic].irqdomain;
 {
        int irq;
        struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
+       struct mp_pin_info *info = mp_pin_info(ioapic, pin);
 
        /*
         * Don't use irqdomain to manage ISA IRQs because there may be
        irq = irq_find_mapping(domain, pin);
        if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
                irq = alloc_irq_from_domain(domain, gsi, pin);
+
+       if (flags & IOAPIC_MAP_ALLOC) {
+               if (irq > 0)
+                       info->count++;
+               else if (info->count == 0)
+                       info->set = 0;
+       }
        mutex_unlock(&ioapic_mutex);
 
        return irq > 0 ? irq : -1;
 
 static int mp_irqdomain_create(int ioapic)
 {
+       size_t size;
        int hwirqs = mp_ioapic_pin_count(ioapic);
        struct ioapic *ip = &ioapics[ioapic];
        struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
        struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
 
+       size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
+       ip->pin_info = kzalloc(size, GFP_KERNEL);
+       if (!ip->pin_info)
+               return -ENOMEM;
+
        if (cfg->type == IOAPIC_DOMAIN_INVALID)
                return 0;
 
        ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
                                              (void *)(long)ioapic);
-       if(!ip->irqdomain)
+       if(!ip->irqdomain) {
+               kfree(ip->pin_info);
+               ip->pin_info = NULL;
                return -ENOMEM;
+       }
 
        if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
            cfg->type == IOAPIC_DOMAIN_STRICT)
        nr_ioapics++;
 }
 
+int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
+                    irq_hw_number_t hwirq)
+{
+       int ioapic = (int)(long)domain->host_data;
+       struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
+       struct io_apic_irq_attr attr;
+
+       /*
+        * Skip the timer IRQ if there's a quirk handler installed and if it
+        * returns 1:
+        */
+       if (apic->multi_timer_check &&
+           apic->multi_timer_check(ioapic, virq))
+               return 0;
+
+       /* Get default attribute if not set by caller yet */
+       if (!info->set) {
+               u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
+
+               if (acpi_get_override_irq(gsi, &info->trigger,
+                                         &info->polarity) < 0) {
+                       /*
+                        * PCI interrupts are always polarity one level
+                        * triggered.
+                        */
+                       info->trigger = 1;
+                       info->polarity = 1;
+               }
+               info->node = NUMA_NO_NODE;
+               info->set = 1;
+       }
+       set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
+                            info->polarity);
+
+       return io_apic_setup_irq_pin(virq, info->node, &attr);
+}
+
+int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
+{
+       int ret = 0;
+       int ioapic, pin;
+       struct mp_pin_info *info;
+
+       ioapic = mp_find_ioapic(gsi);
+       if (ioapic < 0)
+               return -ENODEV;
+
+       pin = mp_find_ioapic_pin(ioapic, gsi);
+       info = mp_pin_info(ioapic, pin);
+       trigger = trigger ? 1 : 0;
+       polarity = polarity ? 1 : 0;
+
+       mutex_lock(&ioapic_mutex);
+       if (!info->set) {
+               info->trigger = trigger;
+               info->polarity = polarity;
+               info->node = node;
+               info->set = 1;
+       } else if (info->trigger != trigger || info->polarity != polarity) {
+               ret = -EBUSY;
+       }
+       mutex_unlock(&ioapic_mutex);
+
+       return ret;
+}
+
 /* Enable IOAPIC early just for system timer */
 void __init pre_init_apic_IRQ0(void)
 {