Modifications for 1.1.6:
======================================================================
+* Series of patches by Erik Theisen, 5 Mar 2002:
+
+ #1: - allow generation of GNU stabs line number debugging symbols
+ for assembly sources ; this allows symbolic debugging of
+ assembly files.
+ - fix probelms due to CYGWIN patches
+ #2: - Fix BEDBUG lossage when using GPR 0 in assembly mode.
+ - Allow BEDBUG to have a choice in whitespace between operand
+ delimiters.
+ - All PPC40x targets had the wrong cacheline size defined in
+ their config files. It should be 32 bytes for 405's and 16
+ bytes for CPUs prior to the 405.
+ - Make sure boards don't use deprecated CONFIG_4xx anymore.
+ - Make sure 405 MAL Ethernet buffer descriptors are malloc'd
+ and aligned on cache boundaries instead of being located at
+ a hard coded address. This was causing lossage on boards
+ with less than 16MB of RAM.
+ - IBM Walnut boards use 33.3Mhz clocks. Prevents rounding.
+ - Added a couple of 4xx specific defines.
+ #3: - Fix compiler warnings
+ - Make sure inline assembly statements properly flag
+ registers that are being modified.
+ #4: - cleanup of common/cmd_i2c.c; eliminated board specific
+ conditionals; eliminated deprecated CONFIG_I2C405 config
+ option.
+ - Added _i2c_bus_reset function to ${CPU}/ppc4xx/i2c.c to
+ handle reset edge condition which was causing EEPROM data
+ corruption. See doc/I2C_Edge_Conditions for details.
+ #5: - Add generic SDRAM SPD, "Serial presence detect," routines.
+ These should work with any 405 based boards that are using
+ SPD.
+ - Make IBM Walnut target use these new routines.
+ - Added ablility to place initial stack into 405's OCM, "On
+ Chip Memory."
+ - Added resetvec address to initial stack to aid in debugging
+ and also cause a reset in the event of an underflow.
+ #6: - Add digital temperature and thermostat support
+ - Add support for Dallas DS1621 and On Semi's LM75 DTTs.
+ - Add command to support the DTTs.
+
+* Add support for >2MB of flash memory on FADS boards
+ Patch by Laurent Pinchart, 05 Mar 2002
+
* Cleanup: enable warnings about uninitialized variables, and fix
most warnings; remove trailing white space; remove (some) C++
comments (it's hopeless, I guess); reformatted some especially ugly
-e s/powerpc/ppc/ \
-e s/macppc/ppc/)
-HOSTOS := $(shell uname -s | tr A-Z a-z)
+HOSTOS := $(shell uname -s | tr A-Z a-z | \
+ sed -e 's/\(cygwin\).*/cygwin/')
ifndef CROSS_COMPILE
ifeq ($(HOSTARCH),ppc)
fs \
net \
rtc \
+ dtt \
examples
#########################################################################
OBJS += net/libnet.a disk/libdisk.a rtc/librtc.a
+OBJS += dtt/libdtt.a
+
OBJS += board/$(BOARDDIR)/lib$(BOARD).a \
cpu/$(CPU)/lib$(CPU).a \
$(ARCH)/lib$(ARCH).a
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F640J5 :
printf ("28F640J5 \n"); break;
- default: printf ("Unknown Chip Type=0x%lXh
-\n",info->flash_id & FLASH_TYPEMASK); break;
+ default: printf ("Unknown Chip Type=0x%lXh\n",
+ info->flash_id & FLASH_TYPEMASK); break;
}
printf (" Size: %ld MB in %d Sectors\n",
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long total_size;
unsigned long size_b0, size_b1;
int i;
flash_info[i].flash_id = FLASH_UNKNOWN;
}
- /* Static FLASH Bank configuration here - FIXME XXX */
+ total_size = 0;
+ size_b0 = 0xffffffff;
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
{
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
- }
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
- if (FLASH_BASE1_PRELIM != 0x0) {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+ if (flash_info[i].flash_id == FLASH_UNKNOWN)
+ {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1>>20);
+ }
+ /* Is this really needed ? - LP */
if (size_b1 > size_b0) {
- printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
+ printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n",
+ i, size_b1, size_b1>>20, i-1, size_b0, size_b0>>20);
+ goto out_error;
}
- } else {
- size_b1 = 0;
+ size_b0 = size_b1;
+ total_size += size_b1;
}
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR0_PRELIM;
- memctl->memc_br0 = CFG_BR0_PRELIM;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ /* Compute the Address Mask */
+ for (i=0; (total_size >> i) != 0; ++i) {};
+ i--;
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+ if (total_size != (1 << i)) {
+ printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n",
+ total_size, total_size>>20);
+ }
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = ((((unsigned long)~1) << i) & OR_AM_MSK) | CFG_OR_TIMING_FLASH;
+ memctl->memc_br0 = CFG_BR0_PRELIM;
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
+ total_size = 0;
- if (size_b1)
+ for (i=0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i)
{
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
-
/* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
+ /* Why ? - LP */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
- flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+ /* This is done by flash_get_size - LP */
+ /* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
- &flash_info[1]);
+ &flash_info[i]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- &flash_info[1]);
+ &flash_info[i]);
#endif
- }
- else
- {
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
+ total_size += size_b1;
}
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
+ return (total_size);
+
+out_error:
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+ {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
- return (size_b0 + size_b1);
+ return (0);
}
/*-----------------------------------------------------------------------
{
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
- break;
+ break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
- break;
+ break;
default:
info->flash_id = FLASH_UNKNOWN;
}
}
#else
- flash_get_offsets ((ulong)addr, &flash_info[0]);
+ flash_get_offsets ((ulong)addr, info);
#endif
/* check for protected sectors */
/* Update entry information.
*/
- rx_new = (++rx_new) % rxRingSize;
+ rx_new = (rx_new + 1) % rxRingSize;
}
return length;
}
}
- Done:
+Done:
+ return;
}
static void send_setup_frame(bd_t *bis)
le32_to_cpu(tx_ring[tx_new].status));
}
#endif
- out:
+out:
+ return;
}
/* SROM Read.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+long int spd_sdram(void);
#include <ppcboot.h>
#include "walnut405.h"
#include <asm/processor.h>
-#include <405_dimm.h>
+
int board_pre_init (void)
------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- return walnut_dimm();
+ long int ret;
+ ret = spd_sdram();
+ return ret;
}
/* ------------------------------------------------------------------------- */
COBJS = board.o main.o command.o environment.o bedbug.o \
cmd_autoscript.o cmd_bedbug.o cmd_boot.o \
cmd_bootm.o cmd_cache.o cmd_console.o cmd_date.o \
- cmd_dcr.o cmd_doc.o cmd_eeprom.o cmd_elf.o \
+ cmd_dcr.o cmd_doc.o cmd_dtt.o cmd_eeprom.o cmd_elf.o \
cmd_fdc.o cmd_flash.o cmd_i2c.o cmd_ide.o \
cmd_immap.o cmd_jffs2.o cmd_mem.o cmd_mii.o \
cmd_misc.o cmd_net.o cmd_nvedit.o cmd_pcmcia.o \
}
if(( param = parse_operand( memaddr, opc, oper[ n_operands ],
- scratch, err )) == 0 )
+ scratch, err )) == -1 )
return 0;
instr |= param;
data = read_number( txt );
if( data > 31 ) {
if( err ) *err = E_ASM_BAD_REGISTER;
- return 0;
+ return -1;
}
data = htonl( data );
else if( oper->hint & OH_SPR ) {
if(( data = spr_value( txt )) == 0 ) {
if( err ) *err = E_ASM_BAD_SPR;
- return 0;
+ return -1;
}
}
else if( oper->hint & OH_TBR ) {
if(( data = tbr_value( txt )) == 0 ) {
if( err ) *err = E_ASM_BAD_TBR;
- return 0;
+ return -1;
}
}
}
/* Find the text of the word */
- while( *ptr && !isblank( *ptr ))
+ while( *ptr && !isblank( *ptr ) && (*ptr != ','))
dest[ nchars++ ] = *ptr++;
+ ptr = (*ptr == ',') ? ptr + 1 : ptr;
dest[ nchars ] = 0;
*src = ptr;
#if defined(CONFIG_BAB750)
#include <w83c553f.h>
#endif
+#include <dtt.h>
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
WATCHDOG_RESET();
+ /* Digital Thermometers and Thermostats */
+#if defined(CONFIG_DTT)
+ dtt_init();
+#endif
+
puts ("DRAM: ");
if ((dram_size = initdram (board_type)) > 0) {
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <config.h>
+#include <command.h>
+#include <cmd_dtt.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_DTT)
+
+#include <dtt.h>
+
+int do_dtt( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] )
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+
+ /*
+ * Loop through sensors, read
+ * temperature, and output it.
+ */
+ for (i = 0; i < sizeof(sensors); i++) {
+ printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
+ }
+
+ return 0;
+} /* do_dtt() */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_DTT */
+
unsigned char i2c_addr, sec_addr, *data_addr;
unsigned short size;
int speed;
-
-
-
-#if !defined(CONFIG_CPCI405) && !defined(CONFIG_AR405) && \
- !defined(CONFIG_I2C405) && !defined(CONFIG_W7O) && \
- !defined (CONFIG_WALNUT405) && !defined (CONFIG_ERIC) && !defined (CONFIG_MPC824X)
-
+ int rc;
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
i2c_state_t state;
#endif
- int rc;
-
switch (argc) {
case 0:
case 2:
if (strncmp (argv[1], "res", 3) == 0) {
printf ("I2C reset 50kHz ... ");
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
+#if defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X)
i2c_init ();
#else
i2c_init (50000, 0xfe); /* use all one's as slave address */
printf ("I2C reset %d.%03dkHz ... ", speed/1000, speed%1000);
else
printf ("I2C reset %dkHz ... ", speed/1000);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
+#if defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X)
i2c_init ();
#else
i2c_init (speed, 0xfe); /* use all one's as slave address */
#endif
, i2c_addr, (ulong)data_addr, size);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || (CONFIG_MPC824X)
-
-#else
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
i2c_newio (&state);
#endif
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC)
-
+#if defined(CONFIG_I2C_4XX)
rc = i2c_receive (i2c_addr, size, data_addr);
+#elif defined(CONFIG_MPC824X)
+ rc = i2c_receive (i2c_addr, 0, size, data_addr);
#else
-#if !defined(CONFIG_MPC824X)
-
rc = i2c_receive (&state, i2c_addr, 0,
I2CF_START_COND|I2CF_STOP_COND,
size, data_addr);
-#else
-
- rc = i2c_receive (i2c_addr, 0, size, data_addr);
-#endif
#endif
return 1;
}
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
-
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
rc = i2c_doio (&state);
#endif
"size %u ... ", i2c_addr, (ulong)data_addr, size);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
i2c_newio (&state);
#endif
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC)
-
+#if defined(CONFIG_I2C_4XX)
rc = i2c_send (i2c_addr, size, data_addr);
+#elif defined(CONFIG_MPC824X)
+ rc = i2c_send (i2c_addr, 0, size, data_addr);
#else
-
-#if !defined(CONFIG_MPC824X)
rc = i2c_send (&state, i2c_addr, 0,
I2CF_START_COND|I2CF_STOP_COND, size, data_addr);
-#else
- rc = i2c_send (i2c_addr, 0, size, data_addr);
-#endif
#endif
if (rc) {
printf ("i2c_receive FAILED rc=%d\n", rc);
return 1;
}
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
-
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
rc = i2c_doio (&state);
#endif
"data_addr 0x%08lx, size %u ... ",
i2c_addr, sec_addr, (ulong)data_addr, size);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
i2c_newio (&state);
#endif
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC)
-
+#if defined(CONFIG_I2C_4XX)
rc = i2c_receive (i2c_addr, size, data_addr);
+#elif defined(CONFIG_MPC824X)
+ rc = i2c_receive (i2c_addr, sec_addr, size, data_addr);
#else
-#if !defined(CONFIG_MPC824X)
-
rc = i2c_receive (&state, i2c_addr, sec_addr,
I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND,
size, data_addr);
-#else
- rc = i2c_receive (i2c_addr, sec_addr, size, data_addr);
-#endif
#endif
if (rc) {
return 1;
}
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
-
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
rc = i2c_doio (&state);
#endif
"data_addr 0x%08lx, size %u ... ",
i2c_addr, sec_addr, (ulong)data_addr, size);
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
i2c_newio (&state);
#endif
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC)
-
+#if defined(CONFIG_I2C_4XX)
rc = i2c_send (i2c_addr, size, data_addr);
+#elif defined(CONFIG_MPC824X)
+ rc = i2c_send (i2c_addr, sec_addr, size, data_addr);
#else
-#if !defined(CONFIG_MPC824X)
rc = i2c_send (&state, i2c_addr, sec_addr,
I2CF_ENABLE_SECONDARY|I2CF_START_COND|I2CF_STOP_COND,
size, data_addr);
-#else
- rc = i2c_send (i2c_addr, sec_addr, size, data_addr);
-#endif
#endif
if (rc) {
return 1;
}
-#if defined(CONFIG_CPCI405) || defined(CONFIG_AR405) || \
- defined(CONFIG_I2C405) || defined(CONFIG_W7O) || \
- defined (CONFIG_WALNUT405) || defined (CONFIG_ERIC) || defined (CONFIG_MPC824X)
-
-#else
-
+#if !(defined(CONFIG_I2C_4XX) || defined (CONFIG_MPC824X))
rc = i2c_doio (&state);
#endif
#include <cmd_bsp.h> /* board special functions */
#include <cmd_bedbug.h>
+#include <cmd_elf.h>
+#include <cmd_dtt.h>
/*
* HELP command
CMD_TBL_DIS
CMD_TBL_DOCBOOT
CMD_TBL_DOC
+ CMD_TBL_DTT
CMD_TBL_ECHO
CMD_TBL_EEPROM
CMD_TBL_FCCINFO
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
endif
-AFLAGS_DEBUG := -Wa,--gstabs
-AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) # $(AFLAGS_DEBUG)
+AFLAGS_DEBUG := -Wa,-gstabs
+AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
#########################################################################
%.s: %.S
- $(CPP) $(AFLAGS) -o $@ $<
+ $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$<
%.o: %.S
- $(CC) $(AFLAGS) -c -o $@ $<
+ $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$<
%.o: %.c
$(CC) $(CFLAGS) -c -o $@ $<
{
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
- __asm__ __volatile__
- ("\n\
- mtspr 26,%0
- li 4,(1<<6)
- mtspr 27,4
- rfi
- " : : "r" (addr));
+
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+
while(1); /* not reached */
}
{
ulong addr;
/* flush and disable I/D cache */
- __asm__ __volatile__
- ("\n\
- mfspr 3,1008
- ori 5,5,0xcc00
- ori 4,3,0xc00
- andc 5,3,5
- sync
- mtspr 1008,4
- isync
- sync
- mtspr 1008,5
- isync
- sync
- ");
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
#ifdef CFG_RESET_ADDRESS
addr = CFG_RESET_ADDRESS;
+-----------------------------------------------------------------------------*/
static volatile mal_desc_t *tx;
static volatile mal_desc_t *rx;
+static mal_desc_t *alloc_tx_buf = NULL;
+static mal_desc_t *alloc_rx_buf = NULL;
/* IER globals */
static unsigned long emac_ier;
/* set the Mal configuration reg */
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* set up the TX and RX descriptors */
- if (first_init == 0) {
- tx = (mal_desc_t *) malloc (4 * NUM_TX_BUFF * sizeof (mal_desc_t));
- rx = (mal_desc_t *) malloc (4 * NUM_RX_BUFF * sizeof (mal_desc_t));
+ /* Free "old" buffers */
+ if (alloc_tx_buf) free(alloc_tx_buf);
+ if (alloc_rx_buf) free(alloc_rx_buf);
+
+ /*
+ * Malloc MAL buffer desciptors, make sure they are
+ * aligned on cache line boundary size
+ * (401/403/IOP480 = 16, 405 = 32)
+ * and doesn't cross cache block boundaries.
+ */
+ alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
+ ((2 * CFG_CACHELINE_SIZE) - 2));
+ if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
+ tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
+ ((int)alloc_tx_buf & CACHELINE_MASK));
+ } else {
+ tx = alloc_tx_buf;
+ }
+
+ alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
+ ((2 * CFG_CACHELINE_SIZE) - 2));
+ if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
+ rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
+ ((int)alloc_rx_buf & CACHELINE_MASK));
+ } else {
+ rx = alloc_rx_buf;
}
for (i = 0; i < NUM_TX_BUFF; i++) {
START = start.o resetvec.o kgdb.o
AOBJS = dcr.o
COBJS = traps.o serial.o cpu.o cpu_init.o speed.o interrupts.o \
- 405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o 405_dimm.o
+ 405gp_pci.o 405gp_enet.o miiphy.o i2c.o bedbug_405.o \
+ spd_sdram.o
OBJS = $(AOBJS) $(COBJS)
all: .depend $(START) $(LIB)
#define IIC_TIMEOUT 1 /* 1 seconde */
+/*
+ * Handle page write settings.
+ */
+#ifndef CFG_EEPROM_PAGE_WRITE_BITS
+#define CFG_EEPROM_PAGE_WRITE_BITS 0
+#endif
+
/* Ensure I/O operations complete */
/* __asm__ volatile("eieio"); */
+
+static void _i2c_bus_reset(void)
+{
+ int i, status;
+
+ /* first clear out status registers */
+ out8(IIC_STS, 0x0A);
+ out8(IIC_EXTSTS, 0x8F);
+ __asm__ volatile("eieio");
+
+ /*
+ * Get current state, reset bus
+ * only if no transfers are pending.
+ */
+ i = 10;
+ do {
+ /* Get status */
+ status = in8(IIC_STS);
+ udelay(500); /* 500us */
+ i--;
+ } while ((status & IIC_STS_PT) && (i>0));
+ /* Soft reset controller */
+ status = in8(IIC_XTCNTLSS);
+ out8(IIC_XTCNTLSS, (status | 0x1));
+ __asm__ volatile("eieio");
+
+ /* make sure where in initial state, data hi, clock hi */
+ out8(IIC_DIRECTCNTL, 0xC);
+ for (i = 0; i < 10; i++){
+ if ((in8(IIC_DIRECTCNTL) & 0x3) != 0x3){
+ /* clock until we get to known state */
+ out8(IIC_DIRECTCNTL, 0x8); /* clock lo */
+ udelay(100); /* 100us */
+ out8(IIC_DIRECTCNTL, 0xC); /* clock hi */
+ udelay(100); /* 100us */
+ } else {
+ break;
+ }
+ }
+ /* send start condition */
+ out8(IIC_DIRECTCNTL, 0x4);
+ udelay(1000); /* 1ms */
+ /* send stop condition */
+ out8(IIC_DIRECTCNTL, 0xC);
+ udelay(1000); /* 1ms */
+ /* Unreset controller */
+ out8(IIC_XTCNTLSS, (status & ~0x1));
+ udelay(1000); /* 1ms */
+}
+
void i2c_init(void)
{
PPC405_SYS_INFO sysInfo;
unsigned long freqOPB;
- int divisor;
+ int val, divisor;
+
+ /* Reset status register */
+ /* write 1 in SCMP and IRQA to clear these fields */
+ out8(IIC_STS, 0x0A);
+
+ /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
+ out8(IIC_EXTSTS, 0x8F);
+
+ /* Handle possible failed I2C state */
+ _i2c_bus_reset();
/* clear lo master address */
out8(IIC_LMADR,0);
- __asm__ volatile("eieio");
+
/* clear hi master address */
out8(IIC_HMADR,0);
- __asm__ volatile("eieio");
+
/* clear lo slave address */
out8(IIC_LSADR,0);
- __asm__ volatile("eieio");
+
/* clear hi slave address */
out8(IIC_HSADR,0);
- __asm__ volatile("eieio");
-
- /* Reset status register */
- /* write 1 in SCMP IRQA to clear these fields */
- /* !!! ASH QpenBios says 0x08 */
- /* out8(IIC_STS, 0x0C); */
- out8(IIC_STS, 0x08);
- __asm__ volatile("eieio");
- /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out8(IIC_EXTSTS, 0x8F);
- __asm__ volatile("eieio");
-
/* Clock divide Register */
/* get OPB frequency */
get_sys_info (&sysInfo);
freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
/* set divisor according to freqOPB */
- divisor = freqOPB / 10000000;
+ divisor = (freqOPB - 1) / 10000000;
if (divisor == 0)
divisor = 1;
out8(IIC_CLKDIV,divisor);
- __asm__ volatile("eieio");
/* no interrupts */
out8(IIC_INTRMSK,0);
- __asm__ volatile("eieio");
+
/* clear transfer count */
out8(IIC_XFRCNT,0);
- __asm__ volatile("eieio");
/* clear extended control & stat */
/* write 1 in SRC SRS SWC SWS to clear these fields */
out8(IIC_XTCNTLSS,0xF0);
- __asm__ volatile("eieio");
/* Mode Control Register
Flush Slave/Master data buffer */
disable interrupts, exit unknown bus state, enable hold
SCL
*/
- out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL));
+ val = in8(IIC_MDCNTL) | IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
__asm__ volatile("eieio");
+ out8(IIC_MDCNTL, val);
/* clear control reg */
out8(IIC_CNTL,0x00);
__asm__ volatile("eieio");
-
}
int bytes_transfered;
int result;
int status;
- int i, TimeReady;
- ulong freqOPB,freqProc;
- ulong TimeOut; /* _must_ be unsigned long for fast speeds */
+ int i;
result = IIC_OK;
bytes_transfered = 0;
do{
/* Get status */
status = in8(IIC_STS);
- __asm__ volatile("eieio");
i--;
}while ((status & IIC_STS_PT) && (i>0));
if (status & IIC_STS_PT)
/* 7-bit adressing */
out8(IIC_HMADR,0);
- __asm__ volatile("eieio");
out8(IIC_LMADR, address);
- __asm__ volatile("eieio");
-
- /* In worst case, you need to wait 4 OPB clocks */
- /* for data being ready on IIC bus */
- /* (because FIFO is 4 bytes depth) */
- freqOPB = get_OPB_freq();
- freqProc = get_gclk_freq();
- TimeReady = (4/(freqProc/freqOPB)) + 1;
-
- /* IIC time out => wait for TimeOut cycles */
- /* TimeOut /= 2; because waiting-loop is 2-instruction loop */
- /* Take care we get no overflow (266MHz = 0x0FDAD680) first divide */
- TimeOut = freqProc/2;
- TimeOut *= IIC_TIMEOUT*10;
while ((bytes_transfered < size_to_transfer) && (result == IIC_OK))
{
if (bytes_transfered == size_to_transfer-1)
{
out8(IIC_CNTL, IIC_CNTL_READ | IIC_CNTL_PT);
- __asm__ volatile("eieio");
}
else
{
out8(IIC_CNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT);
- __asm__ volatile("eieio");
}
}
else
{
/* Set buffer */
out8(IIC_MDBUF,data[bytes_transfered]);
- __asm__ volatile("eieio");
- i=TimeReady;
- do{
- i--;
- }while(i>0);
+ udelay(1);
/* issue write command */
if (bytes_transfered == size_to_transfer-1)
{
out8(IIC_CNTL, IIC_CNTL_PT);
- __asm__ volatile("eieio");
}
else
{
out8(IIC_CNTL, IIC_CNTL_CHT | IIC_CNTL_PT);
- __asm__ volatile("eieio");
}
}
-
-
+ __asm__ volatile("eieio");
/* Transfer is in progress */
- i=TimeOut;
+ i=20;
do{
/* Get status */
status = in8(IIC_STS);
- __asm__ volatile("eieio");
+ udelay(10);
i--;
- }while ((status & IIC_STS_PT) && (i>0));
+ }while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i>0));
- if (status & IIC_STS_PT)
- {
- result = IIC_NOK_TOUT;
- }
- else if (status & IIC_STS_ERR)
+ if (status & IIC_STS_ERR)
{
result = IIC_NOK;
status = in8(IIC_EXTSTS);
- __asm__ volatile("eieio");
/* Lost arbitration? */
if (status & IIC_EXTSTS_LA)
result = IIC_NOK_LA;
if (status & IIC_EXTSTS_XFRA)
result = IIC_NOK_XFRA;
}
+ else if (status & IIC_STS_PT)
+ {
+ result = IIC_NOK_TOUT;
+ }
/* Command is reading => get buffer */
if ((command_is_reading) && (result == IIC_OK))
{
/* Are there data in buffer */
if (status & IIC_STS_MDBS)
{
- i=TimeReady;
- do{
- i--;
- }while(i>0);
+ udelay(1);
data[bytes_transfered] = in8(IIC_MDBUF);
- __asm__ volatile("eieio");
}
else result = IIC_NOK_DATA;
}
{
int status;
status = i2c_transfer(1, address, size_to_expect, datain);
-#ifdef CONFIG_WALNUT405
- if (status != 0) printf("\nI2C error => status = %d\n", status);
-#endif
return status;
}
{
int status;
status = i2c_transfer(0, address, size_to_send, dataout);
-#ifdef CONFIG_WALNUT405
- if (status != 0) printf("\nI2C error => status = %d\n", status);
-#endif
return status;
}
int i2c_read (uchar *addr, int alen, uchar *buffer, int len)
{
- int rcode = 0;
-
if ((alen < 1) || (alen > 3)) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ /* Can't out string when called early in boot process. */
+ /* printf ("I2C read: addr len %d not supported\n", alen); */
return 1;
}
- if (i2c_send (addr[0] << 1, alen-1, addr+1) != 0) rcode = 1;
- if (i2c_receive ((addr[0] << 1) | 0x01, len, buffer) != 0) rcode = 1;
- return rcode;
+ if (i2c_send (addr[0] << 1, alen-1, addr + 1) != 0)
+ return 1;
+
+ if (i2c_receive ((addr[0] << 1) | 0x01, len, buffer) != 0)
+ return 1;
+
+ return 0;
}
-#ifndef CFG_EEPROM_PAGE_WRITE_ENABLE
-int i2c_write (uchar *addr, int alen, uchar *buffer, int len)
+/*
+ * i2c_wr_page() - Write a buffer as a series of pages.
+ * For devices that don't support page writes, pass a 1 as
+ * the page size. For devices that support an infinite
+ * page size, use a page size of 0.
+ */
+#define _I2C_MAX_ADDR_SIZE (sizeof(long))
+int i2c_wr_page (unsigned char *addr, int alen, unsigned char *data, int dlen, int page_size)
{
- uchar xbuf[3];
- unsigned short paddr;
-
- if (alen == 2) {
- /* write with ack polling */
- while (len-- > 0) {
- xbuf[0] = addr[1]++; /* increase write offset */
- xbuf[1] = *buffer++;
- /* single write + ack polling */
- while (i2c_send (addr[0] << 1, 2, xbuf) != 0) {
- udelay(100);
- }
- }
- return 0;
- }
-
- paddr=(addr[1]<<8)+addr[2];
-
- if (alen == 3) {
- /* write with ack polling */
- while (len-- > 0) {
- xbuf[0] = (uchar)(paddr>>8); /* High addr */
- xbuf[1] = (uchar)(paddr&0xff); /* Low addr */
- paddr++;
- xbuf[2] = *buffer++;
- /* single write + ack polling */
- while (i2c_send (addr[0] << 1, 3, xbuf) != 0) {
- udelay(100);
- }
- }
- return 0;
- }
-
- printf ("I2C write: addr len %d not supported\n", alen);
- return 1;
-}
+ unsigned long idx, i, offset = 0;
+ unsigned char *data_ptr = data;
+ unsigned char xbuf[_I2C_MAX_ADDR_SIZE + (1 << CFG_EEPROM_PAGE_WRITE_BITS)];
+
+ /* Validate parameters. */
+ if ((alen < 1) || (alen > _I2C_MAX_ADDR_SIZE) ||
+ (dlen < 0) || (page_size > 20))
+ return 1;
+
+ /* create a cardinal address from the address char array */
+ /* why do we go through all this trouble converting to cardinal
+ and then back to array? so we can have address wrap correctly
+ when we reach a 256 byte boundry on large parts. */
+ for (i = 0; i < alen; i++)
+ offset = (offset << 8) + addr[i];
+
+ /* write with ack polling */
+ while (dlen > 0) {
+ /* reset pointers */
+ idx = 0;
+
+ /* move the address bytes into array, msb first */
+ for (i = alen; i > 0; i--) {
+ xbuf[idx++] = (unsigned char)((offset>>((i-1)*8)) & 0xff);
+ }
+
+ /*
+ * Move the data to output buffer
+ * stop when we reach end of page, or
+ * when all data is sent
+ */
+ do {
+ xbuf[idx++] = *data_ptr++;
+ offset++;
+ dlen--;
+ } while (((page_size == 0) || (offset % page_size)) && (dlen > 0));
+
+ /*
+ * Write the page, i2c expects the 1st address byte
+ * to be handled specialy, so we separate it out,
+ * inc the pointer, and dec the len
+ */
+ i2c_send(xbuf[0] << 1, idx - 1, xbuf + 1);
+ udelay(100);
+
+ /*
+ * Wait for completion, we use a short msg and look for ack,
+ * when we get an ack, the i2c is finished, and returns 0.
+ *
+ * FIXME - Needs timeout error handling.
+ */
+ while ((i2c_send(xbuf[0] << 1, 1, xbuf + 1)) != 0) {
+ udelay(100);
+ }
+ }
+ return 0;
+} /* i2c_wr_page() */
-#else /* CFG_EEPROM_PAGE_WRITE_ENABLE */
int i2c_write (uchar *addr, int alen, uchar *buffer, int len)
{
- /* buffer for one page + addresses */
- uchar wbuffer[(1<<CFG_EEPROM_PAGE_WRITE_BITS)+2];
-
- int i;
-
- if (alen == 2) {
- /* fill in address first */
- wbuffer[0] = addr[1];
- for (i=1; i < len+1; i++) {
- wbuffer[i] = *buffer++; /* copy data */
- }
- /* write page + ack polling */
- while (i2c_send (addr[0] << 1, len+1, wbuffer) != 0) {
- udelay(100);
- }
- return 0;
- }
- if (alen == 3) {
- /* fill in the address first */
- wbuffer[0] = addr[1];
- wbuffer[1] = addr[2];
- for (i=2; i < len+2; i++) {
- wbuffer[i] = *buffer++; /* copy data */
- }
- /* write page + ack polling */
- while (i2c_send (addr[0] << 1, len+2, wbuffer) != 0) {
- udelay(100);
- }
- return 0;
- }
- printf ("I2C write: addr len %d not supported\n", alen);
- return 1;
-}
-#endif /* CFG_EEPROM_PAGE_WRITE_ENABLE */
-
+ return i2c_wr_page(addr, alen, buffer, len, 1 << CFG_EEPROM_PAGE_WRITE_BITS);
+} /* i2c_write() */
-int i2c_write_page (uchar *addr, int alen, uchar *data, int dlen, int dsize)
-{
- uchar xbuf[7];
- int idx, i;
-
- /* Validate parameters. */
- if (alen > 3) {
- printf("I2C write: addr len %d not supported\n", alen);
- return 1;
- }
- if (dsize > 4) {
- printf ("I2C write: data size %d not supported\n", dsize);
- return 1;
- }
-
- /* write with ack polling */
- while (dlen > 0) {
- /* build up an output buffer */
- idx = 0;
-
- /* move the extra address bytes to buffer */
- for (i = 1; i < alen; i++)
- xbuf[idx++] = addr[i];
-
- /* move the data to output buffer */
- for (i = 0; ((i < dsize) && (dlen-- > 0)); i++)
- xbuf[idx++] = *data++;
-
- /* single write + ack polling */
- while ((i2c_send(addr[0] << 1, idx, xbuf)) != 0) {
- udelay(100);
- }
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
+ *
+ * Based on code by:
+ *
+ * Kenneth Johansson ,Ericsson Business Innovation.
+ * kenneth.johansson@inn.ericsson.se
+ *
+ * hacked up by bill hunter. fixed so we could run before
+ * serial_init and console_init. previous version avoided this by
+ * running out of cache memory during serial/console init, then running
+ * this code later.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <ppc4xx.h>
+
+#ifdef CONFIG_SPD_EEPROM
+
+#define SDRAM0_CFG_DCE 0x80000000
+#define SDRAM0_CFG_SRE 0x40000000
+#define SDRAM0_CFG_PME 0x20000000
+#define SDRAM0_CFG_MEMCHK 0x10000000
+#define SDRAM0_CFG_REGEN 0x08000000
+#define SDRAM0_CFG_ECCDD 0x00400000
+#define SDRAM0_CFG_EMDULR 0x00200000
+#define SDRAM0_CFG_DRW_SHIFT (31-6)
+#define SDRAM0_CFG_BRPF_SHIFT (31-8)
+
+#define SDRAM0_TR_CASL_SHIFT (31-8)
+#define SDRAM0_TR_PTA_SHIFT (31-13)
+#define SDRAM0_TR_CTP_SHIFT (31-15)
+#define SDRAM0_TR_LDF_SHIFT (31-17)
+#define SDRAM0_TR_RFTA_SHIFT (31-29)
+#define SDRAM0_TR_RCD_SHIFT (31-31)
+
+#define SDRAM0_RTR_SHIFT (31-15)
+#define SDRAM0_ECCCFG_SHIFT (31-11)
+
+/* SDRAM0_CFG enable macro */
+#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
+
+#define SDRAM0_BXCR_SZ_MASK 0x000e0000
+#define SDRAM0_BXCR_AM_MASK 0x0000e000
+
+#define SDRAM0_BXCR_SZ_SHIFT (31-14)
+#define SDRAM0_BXCR_AM_SHIFT (31-18)
+
+#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
+#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
+
+#ifdef config_WALNUT405
+# define SPD_ERR(x) {printf(x); hang()};
+#else
+# define SPD_ERR(x) return 0;
+#endif
+
+/*
+ * what we really want is
+ * (1/hertz) but we don't want to use floats so multiply with 10E9
+ *
+ * The error needs to be on the safe side so we want the floor function.
+ * This means we get an exact value or we calculate that our bus frequency is
+ * a bit faster than it really is and thus we don't progam the sdram controller
+ * to run to fast
+ */
+#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
+
+/* function prototypes */
+int spd_read( int x ); /* prototype */
+
+
+/*
+ * This function is reading data from the DIMM module EEPROM over the SPD bus
+ * and uses that to program the sdram controller.
+ *
+ * This works on boards that has the same schematics that the IBM walnut has.
+ *
+ * BUG: Don't handle ECC memory
+ * BUG: A few values in the TR register is currently hardcoded
+ */
+
+long int spd_sdram(void)
+{
+ int bus_period,tmp,row,col;
+ int total_size,bank_size,bank_code;
+ int bank_cnt,ecc_on,mode;
+
+ int sdram0_pmit=0x07c00000;
+ int sdram0_besr0=-1;
+ int sdram0_besr1=-1;
+ int sdram0_eccesr=-1;
+ int sdram0_ecccfg;
+
+ int sdram0_rtr=0;
+ int sdram0_tr=0;
+
+ int sdram0_b0cr;
+ int sdram0_b1cr;
+ int sdram0_b2cr;
+ int sdram0_b3cr;
+
+ int sdram0_cfg=0;
+
+ int t_rp;
+ int t_rcd;
+ int t_rc = 70; /* This value not available in SPD_EEPROM */
+ int min_cas;
+#if defined(CONFIG_WALNUT405)
+ PPC405_SYS_INFO sys_info;
+#endif
+
+
+#if defined(CONFIG_W7O)
+ tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
+ tmp = CONFIG_SYS_CLK_FREQ * tmp; /* get plb freq */
+ bus_period = sdram_HZ_to_ns(tmp); /* get sdram speed */
+#elif defined(CONFIG_WALNUT405)
+ get_sys_info(&sys_info);
+ bus_period = sdram_HZ_to_ns(sys_info.freqPLB );
+#endif
+
+ /* Make shure we are using SDRAM */
+ if (spd_read(2) != 0x04){
+ SPD_ERR("SDRAM - non SDRAM memory module found\n");
+ }
+
+/*------------------------------------------------------------------
+ configure memory timing register
+
+ data from DIMM:
+ 27 IN Row Precharge Time ( t RP)
+ 29 MIN RAS to CAS Delay ( t RCD)
+ 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
+ -------------------------------------------------------------------*/
+
+ /*
+ * first figure out which cas latency mode to use
+ * use the min supported mode
+ */
+
+ tmp = spd_read(127) & 0x6;
+ if(tmp == 0x02){ /* only cas = 2 supported */
+ min_cas = 2;
+// t_ck = spd_read(9);
+// t_ac = spd_read(10);
+ }
+ else if (tmp == 0x04){ /* only cas = 3 supported */
+ min_cas = 3;
+// t_ck = spd_read(9);
+// t_ac = spd_read(10);
+ }
+ else if (tmp == 0x06){ /* 2,3 supported, so use 2 */
+ min_cas = 2;
+// t_ck = spd_read(23);
+// t_ac = spd_read(24);
+ }
+ else {
+ SPD_ERR("SDRAM - unsupported CAS latency \n");
+ }
+
+ /* get some timing values, t_rp,t_rcd
+ */
+ t_rp = spd_read(27);
+ t_rcd = spd_read(29);
+
+
+ /* The following timing calcs subtract 1 before deviding.
+ * this has effect of using ceiling intead of floor rounding,
+ * and also subtracting 1 to convert number to reg value
+ */
+ /* set up CASL */
+ sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
+ /* set up PTA */
+ sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
+ /* set up CTP */
+ tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
+ if(tmp<1) SPD_ERR("SDRAM - unsupported prech to act time (Trp)\n");
+ sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
+ /* set LDF = 2 cycles, reg value = 1 */
+ sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
+ /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
+ tmp = ((t_rc - 1) / bus_period)-4;
+ if(tmp<0)tmp=0;
+ if(tmp>6)tmp=6;
+ sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
+ /* set RCD = t_rcd/bus_period*/
+ sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
+
+
+/*------------------------------------------------------------------
+ configure RTR register
+ -------------------------------------------------------------------*/
+ row = spd_read(3);
+ col = spd_read(4);
+ tmp = spd_read(12) & 0x7f ; /* refresh type less self refresh bit */
+ switch(tmp){
+ case 0x00:
+ tmp=15625;
+ break;
+ case 0x01:
+ tmp=15625/4;
+ break;
+ case 0x02:
+ tmp=15625/2;
+ break;
+ case 0x03:
+ tmp=15625*2;
+ break;
+ case 0x04:
+ tmp=15625*4;
+ break;
+ case 0x05:
+ tmp=15625*8;
+ break;
+ default:
+ SPD_ERR("SDRAM - Bad refresh period \n");
+ }
+ /* convert from nsec to bus cycles */
+ tmp = tmp/bus_period;
+ sdram0_rtr = (tmp & 0x3ff8)<< SDRAM0_RTR_SHIFT;
+
+/*------------------------------------------------------------------
+ determine the number of banks used
+ -------------------------------------------------------------------*/
+ /* byte 7:6 is module data width */
+ if(spd_read(7) != 0)
+ SPD_ERR("SDRAM - unsupported module width\n")
+ tmp = spd_read(6);
+ if (tmp < 32)
+ SPD_ERR("SDRAM - unsupported module width\n")
+ else if (tmp < 64)
+ bank_cnt=1; /* one bank per sdram side */
+ else if (tmp < 73)
+ bank_cnt=2; /* need two banks per side */
+ else if (tmp < 161)
+ bank_cnt=4; /* need four banks per side */
+ else
+ SPD_ERR("SDRAM - unsupported module width\n")
+
+ /* byte 5 is the module row count (refered to as dimm "sides") */
+ tmp = spd_read(5);
+ if(tmp==1);
+ else if(tmp==2) bank_cnt *=2;
+ else if(tmp==4) bank_cnt *=4;
+ else bank_cnt = 8; /* 8 is an error code */
+
+ if(bank_cnt > 4) /* we only have 4 banks to work with */
+ SPD_ERR("SDRAM - unsupported module rows for this width\n");
+
+ /* now check for ECC ability of module. We only support ECC
+ * on 32 bit wide devices with 8 bit ECC.
+ */
+ if ( (spd_read(11)==2) && ((spd_read(6)==40) || (spd_read(14)==8)) ){
+ sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
+ ecc_on = 1;
+ }
+ else{
+ sdram0_ecccfg=0;
+ ecc_on = 0;
+ }
+
+/*------------------------------------------------------------------
+ calculate total size and do sanity check
+ -------------------------------------------------------------------*/
+ /* calculate total size and do sanity check */
+ tmp = spd_read(31);
+ total_size=1<<22; /* total_size = 4MB */
+ /* now multiply 4M by the smallest device roe density */
+ /* note that we don't support asymetric rows */
+ while (((tmp & 0x0001) == 0) && (tmp != 0)){
+ total_size= total_size<<1;
+ tmp = tmp>>1;
+ }
+ total_size *= spd_read(5); /* mult by module rows (dimm sides) */
+ /* now compute Total size based on address bits */
+ tmp = 1 << (row+col); /* convert rows and cols to size */
+ tmp *= spd_read(6)/8; /* mult by bus width in bytes */
+ tmp *= spd_read(17); /* mult by internal banks */
+ /* see if the two methods of calculating size agree */
+ if ( tmp != total_size)
+ SPD_ERR("SDRAM - conflicting module memory size\n");
+
+/*------------------------------------------------------------------
+ map rows * cols * banks to a mode
+ -------------------------------------------------------------------*/
+
+ switch( row )
+ {
+ case 11:
+ switch ( col )
+ {
+ case 8:
+ mode=4; /* mode 5 */
+ break;
+ case 9:
+ case 10:
+ mode=0; /* mode 1 */
+ break;
+ default:
+ SPD_ERR("SDRAM - unsupported mode\n");
+ }
+ break;
+ case 12:
+ switch ( col )
+ {
+ case 8:
+ mode=3; /* mode 4 */
+ break;
+ case 9:
+ case 10:
+ mode=1; /* mode 2 */
+ break;
+ default:
+ SPD_ERR("SDRAM - unsupported mode\n");
+ }
+ break;
+ case 13:
+ switch ( col )
+ {
+ case 8:
+ mode=5; /* mode 6 */
+ break;
+ case 9:
+ case 10:
+ if (spd_read(17) ==2 )
+ mode=6; /* mode 7 */
+ else
+ mode=2; /* mode 3 */
+ break;
+ case 11:
+ mode=2; /* mode 3 */
+ break;
+ default:
+ SPD_ERR("SDRAM - unsupported mode\n");
+ }
+ break;
+ default:
+ SPD_ERR("SDRAM - unsupported mode\n");
+ }
+
+/*------------------------------------------------------------------
+ using the calculated values, compute the bank
+ config register values.
+ -------------------------------------------------------------------*/
+ sdram0_b1cr = 0;
+ sdram0_b2cr = 0;
+ sdram0_b3cr = 0;
+
+ /* compute the size of each bank */
+ bank_size = total_size / bank_cnt;
+ /* convert bank size to bank size code for ppc4xx
+ by takeing log2(bank_size) - 22 */
+ tmp=bank_size; /* start with tmp = bank_size */
+ bank_code=0; /* and bank_code = 0 */
+ while (tmp>1){ /* this takes log2 of tmp */
+ bank_code++; /* and stores result in bank_code */
+ tmp=tmp>>1;
+ } /* bank_code is now log2(bank_size) */
+ bank_code-=22; /* subtract 22 to get the code */
+
+ tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
+ sdram0_b0cr = (bank_size) * 0 | tmp;
+ if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
+ if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
+ if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
+
+
+ /*
+ * enable sdram controller DCE=1
+ * enable burst read prefetch to 32 bytes BRPF=2
+ * leave other functions off
+ */
+
+/*------------------------------------------------------------------
+ now that we've done our calculations, we are ready to
+ program all the registers.
+ -------------------------------------------------------------------*/
+
+
+#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+ /* disable memcontroller so updates work */
+ sdram0_cfg = 0;
+ mtsdram0( mem_mcopt1, sdram0_cfg );
+
+ mtsdram0( mem_besra , sdram0_besr0 );
+ mtsdram0( mem_besrb , sdram0_besr1 );
+ mtsdram0( mem_rtr , sdram0_rtr );
+ mtsdram0( mem_pmit , sdram0_pmit );
+ mtsdram0( mem_mb0cf , sdram0_b0cr );
+ mtsdram0( mem_mb1cf , sdram0_b1cr );
+ mtsdram0( mem_mb2cf , sdram0_b2cr );
+ mtsdram0( mem_mb3cf , sdram0_b3cr );
+ mtsdram0( mem_sdtr1 , sdram0_tr );
+ mtsdram0( mem_ecccf , sdram0_ecccfg );
+ mtsdram0( mem_eccerr, sdram0_eccesr );
+
+ /* SDRAM have a power on delay, 500 micro should do */
+ udelay(500);
+ sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
+ if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+ mtsdram0( mem_mcopt1, sdram0_cfg );
+
+
+ /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
+#ifdef MVISTA_MEM_BUG
+ if (total_size > 128*1024*1024 )
+ total_size=128*1024*1024;
+#endif
+ return (total_size);
+}
+
+int spd_read( int x ){
+ char addr[2];
+ char data[2];
+
+ addr[0]=0x50;
+ addr[1]=(char)x;
+ if (i2c_read(addr,2,data,1) == 0) return (int)data[0];
+ else return 0;
+}
+
+
+#endif /* CONFIG_DIMM_EEPROM */
+
#endif
/*----------------------------------------------------------------------- */
- /* Initialize SDRAM Controller */
+ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
- bl sdram_init
-
#ifdef CFG_INIT_DCACHE_CS
/*----------------------------------------------------------------------- */
/* Memory Bank x (nothingness) initialization 1GB+64MEG */
lis r4,0xdead /* we store 0xdeaddead in the stack */
ori r4,r4,0xdead
-stackloop:
+..stackloop:
stwu r4,-4(r2)
- bdnz stackloop
-#else
- addis r1,r0,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+ bdnz ..stackloop
+
+ li r0, 0 /* Make room for stack frame header and */
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+ /*
+ * Set up a dummy frame to store reset vector as return address.
+ * this causes stack underflow to reset board.
+ */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
+ ori r0, r0, RESET_VECTOR@l
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save return addr (underflow vect) */
+
+#elif defined(CFG_TEMP_STACK_OCM) && \
+ (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
+ /*
+ * Stack in OCM.
+ */
+
+ /* Set up Stack at top of OCM */
+ addis r1, 0, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
+
+ /* Set up a zeroized stack frame so that backtrace works right */
+ li r0, 0
+ stwu r0, -4(r1)
+ stwu r0, -4(r1)
+
+ /*
+ * Set up a dummy frame to store reset vector as return address.
+ * this causes stack underflow to reset board.
+ */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
+ ori r0, r0, RESET_VECTOR@l
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save return addr (underflow vect) */
#endif /* CFG_INIT_DCACHE_CS */
+ /*----------------------------------------------------------------------- */
+ /* Initialize SDRAM Controller */
+ /*----------------------------------------------------------------------- */
+ bl sdram_init
+
+ /*
+ * Setup temporary stack pointer only for boards
+ * that do not use SDRAM SPD I2C stuff since it
+ * is already initialized to use DCACHE or OCM
+ * stacks.
+ */
+#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
+ addis r1,r0,CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+ /*
+ * Set up a dummy frame to store reset vector as return address.
+ * this causes stack underflow to reset board.
+ */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
+ ori r0, r0, RESET_VECTOR@l
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save return addr (underflow vect) */
+#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
+ /* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
#endif /* CONFIG_405GP || CONFIG_405CR */
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
- addi r7,r0, 128 /* do loop for # of dcache lines */
+ /* Do loop for # of dcache congruence classes. */
+ addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
dccci 0,r6 /* invalidate line */
- addi r6,r6, 32 /* bump to next line */
+ addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
bdnz ..dcloop
blr
mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
or r10,r10,r9 /* bit 31 in dccr */
mtdccr r10
- addi r10,r0,128 /* do loop for # of lines */
- addi r11,r0,4096 /* D cache set size=4K */
+
+ /* do loop for # of congruence classes. */
+ addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
+ addi r11,r0,(CFG_DCACHE_SIZE / 2) // D cache set size - 2 way sets
mtctr r10
addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
lwz r3,0(r10) /* least recently used side */
lwz r3,0(r11) /* the other side */
dccci r0,r11 /* invalidate both sides */
- addi r10,r10,0x0020 /* bump to next line (32 bytes) */
- addi r11,r11,0x0020 /* bump to next line (32 bytes) */
+ addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
+ addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
bdnz ..flush_dcache_loop
sync /* allow memory access to complete */
mtdccr r9 /* restore dccr */
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
- blr
+ blr /* NEVER RETURNS! */
in_ram:
--- /dev/null
+I2C Edge Conditions:
+====================
+
+ I2C devices may be left in a write state if a read was occuring
+ and the CPU was reset. This may result in EEPROM data corruption.
+
+ The edge condition is as follows:
+ 1) A read operation begins.
+ 2) I2C controller issues a start command.
+ 3) The I2C writes the device address.
+ 4) The CPU is reset at this point.
+
+ Once the CPU reinitializes and the read is tried again:
+ 1) The I2C controller issues a start command.
+ 2) The I2C controller writes the device address.
+ 3) The I2C controller writes the offset.
+
+ The EEPROM sees:
+ 1) START
+ 2) device address
+ 3) START "this start is ignored by most EEPROMs"
+ 4) device address "EEPROM interprets this as offset"
+ 5) Offset in device, "EEPROM interprets this as data to write"
+
+ The device will interpret this sequence as a WRITE command and
+ write rubbish into itself, i.e. the "offset" will be interpreted
+ as data to be written in location "device address".
+
+Notes
+-----
+!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
+
+This reset edge condition could possibly be present in every I2C
+controller and device available. We should probably have a bus reset
+function for all our target CPUs.
+
+Many thanks to Bill Hunter for finding this serious BUG.
+email to: <williamhunter@attbi.com>
+
+Erik Theisen <etheisen@mindspring.com>
+Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET)
dhcp 4
dmainfo 3
ds 2
+dtt 3
echo 4
eeprom 3
erase 3
--- /dev/null
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+#CFLAGS += -DDEBUG
+
+LIB = libdtt.a
+
+OBJS = lm75.o ds1621.o
+
+all: $(LIB)
+
+$(LIB): $(START) $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat.
+ */
+
+#include <ppcboot.h>
+
+#ifdef CONFIG_DTT_DS1621
+#include <i2c.h>
+#include <dtt.h>
+
+/*
+ * Handle 4xx differences.
+ */
+#if defined(CONFIG_4xx)
+#define I2C_WRITER(addr, addrlen, data, datalen, pgsize) \
+ i2c_wr_page(addr, addrlen, data, datalen, pgsize)
+#else
+#define I2C_WRITER(addr, addrlen, data, datalen, pgsize) \
+ i2c_write(addr, addrlen, data, datalen)
+#endif
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
+
+int dtt_read(int sensor, int reg)
+{
+ int dlen;
+ short status;
+ uchar addr[2];
+ uchar data[2];
+
+ /*
+ * Calculate sensor address and command.
+ *
+ */
+ sensor &= 0x07; /* Only allow sensor 0-7. */
+ addr[0] = DTT_I2C_DEV_CODE + sensor; /* Calculate addr of ds1621*/
+ addr[1] = reg;
+
+ /*
+ * Prepare to handle 2 byte result.
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW))
+ dlen = 2;
+ else
+ dlen = 1;
+
+ /*
+ * Now try to read the register.
+ */
+ if ((status = i2c_read(addr, 2, data, dlen)) != 0)
+ return 1;
+
+ /*
+ * Handle 2 byte result.
+ */
+ if (dlen == 2)
+ return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+ return (int)data[0];
+} /* dtt_read() */
+
+
+int dtt_write(int sensor, int reg, int val)
+{
+ int status, dlen;
+ uchar addr;
+ uchar data[3];
+
+ /*
+ * Calculate sensor address and register.
+ *
+ */
+ sensor &= 0x07; /* only allow sensor 0-7 */
+ addr = DTT_I2C_DEV_CODE + (sensor); /* calculate addr of ds1621 */
+ data[0] = reg; /* address of reg */
+
+ /*
+ * Handle various data sizes.
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) {
+ dlen = 2;
+ data[1] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[2] = (char)(val & 0xff);
+ }
+ else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) {
+ dlen = 0;
+ data[1] = (char)0;
+ data[2] = (char)0;
+ }
+ else {
+ dlen = 1;
+ data[1] = (char)(val & 0xff);
+ }
+
+ /*
+ * Write value to device.
+ */
+ if (I2C_WRITER(&addr, 1, data, dlen, 0) != 0)
+ return 1;
+
+ return 0;
+} /* dtt_write() */
+
+
+static int _dtt_init(int sensor)
+{
+ int val;
+
+ /*
+ * Setup High Temp.
+ */
+ val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup Low Temp - hysteresis.
+ */
+ val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ /*
+ * Setup configuraton register
+ *
+ * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
+ *
+ * We run in polled mode, since there isn't any way to know if this
+ * lousy device is ready to provide temperature readings on power up.
+ */
+ val = 0x9;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+ udelay(50000); /* Max 50ms */
+
+ return 0;
+} /* _dtt_init() */
+
+
+void dtt_init(void)
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i+1);
+ else
+ printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
+ }
+} /* dtt_init() */
+
+
+int dtt_get_temp(int sensor)
+{
+ int i;
+
+ /*
+ * Start a conversion, may take up to 1 second.
+ */
+ dtt_write(sensor, DTT_WRITE_START_CONV, 0);
+ for (i = 0; i <= 10; i++) {
+ udelay(100000);
+ if (dtt_read(sensor, DTT_CONFIG) & 0x80)
+ break;
+ }
+
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+} /* dtt_get_temp() */
+
+
+#endif /* CONFIG_DTT_DS1621 */
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * On Semiconductor's LM75 Temperature Sensor
+ */
+
+#include <ppcboot.h>
+
+#ifdef CONFIG_DTT_LM75
+#include <i2c.h>
+#include <dtt.h>
+
+/*
+ * Handle 4xx differences.
+ */
+#if defined(CONFIG_4xx)
+#define I2C_WRITER(addr, addrlen, data, datalen, pgsize) \
+ i2c_wr_page(addr, addrlen, data, datalen, pgsize)
+#else
+#define I2C_WRITER(addr, addrlen, data, datalen, pgsize) \
+ i2c_write(addr, addrlen, data, datalen)
+#endif
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */
+
+int dtt_read(int sensor, int reg)
+{
+ int dlen;
+ uchar addr[2];
+ uchar data[2];
+
+ /*
+ * Validate 'reg' param
+ */
+ if((reg < 0) || (reg > 3))
+ return -1;
+
+ /*
+ * Calculate sensor address and register.
+ */
+ sensor &= 0x07; /* only allow sensor 0-7 */
+ addr[0] = DTT_I2C_DEV_CODE + sensor; /* calculate address of lm75 */
+ addr[1] = reg; /* address of reg */
+
+ /*
+ * Prepare to handle 2 byte result.
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_HYST) ||
+ (reg == DTT_TEMP_SET))
+ dlen = 2;
+ else
+ dlen = 1;
+
+ /*
+ * Now try to read the register.
+ */
+ if (i2c_read(addr, 2, data, dlen) != 0)
+ return -1;
+
+ /*
+ * Handle 2 byte result.
+ */
+ if (dlen == 2)
+ return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+
+ return (int)data[0];
+} /* dtt_read() */
+
+
+int dtt_write(int sensor, int reg, int val)
+{
+ int dlen;
+ uchar addr;
+ uchar data[3];
+
+ /*
+ * Validate 'reg' param
+ */
+ if ((reg < 0) || (reg > 3))
+ return 1;
+
+ /*
+ * Calculate sensor address and register.
+ *
+ */
+ sensor &= 0x07; /* only allow sensor 0-7 */
+ addr = DTT_I2C_DEV_CODE + (sensor); /* calculate address of lm75 */
+ data[0] = reg; /* address of reg */
+
+ /*
+ * Handle 2 byte values.
+ */
+ if ((reg == DTT_READ_TEMP) ||
+ (reg == DTT_TEMP_HYST) ||
+ (reg == DTT_TEMP_SET)) {
+ dlen = 3;
+ data[1] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[2] = (char)(val & 0xff);
+ } else {
+ dlen = 2;
+ data[1] = (char)(val & 0xff);
+ }
+
+ /*
+ * Write value to register.
+ */
+ if (I2C_WRITER(&addr, 1, data, dlen, 0) != 0)
+ return 1;
+
+ return 0;
+} /* dtt_write() */
+
+
+static int _dtt_init(int sensor)
+{
+ int val;
+
+ /*
+ * Setup TSET ( trip point ) register
+ */
+ val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */
+ if (dtt_write(sensor, DTT_TEMP_SET, val) != 0)
+ return 1;
+
+ /*
+ * Setup THYST ( untrip point ) register - Hysteresis
+ */
+ val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
+ return 1;
+
+ /*
+ * Setup configuraton register
+ */
+ /* config = 6 sample integration, int mode, active low, and enable */
+ val = 0x18;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+
+ return 0;
+} /* _dtt_init() */
+
+
+void dtt_init(void)
+{
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
+ const char *const header = "DTT: ";
+
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("%s%d FAILED INIT\n", header, i+1);
+ else
+ printf("%s%d is %i C\n", header, i+1,
+ dtt_get_temp(sensors[i]));
+ }
+} /* dtt_init() */
+
+int dtt_get_temp(int sensor)
+{
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+} /* dtt_get_temp() */
+
+#endif /* CONFIG_DTT_LM75 */
+
dist += (symbol % 2) << ((symbol - 2) >> 1);
}
stream->decoded += length;
- for (i = 0; i < length; i++) *(dest++) = dest[-dist];
+ for (i = 0; i < length; i++) {
+ *dest = dest[-dist];
+ dest++;
+ }
}
} while (symbol != 256); /* 256 is the end of the data block */
}
#define CFG_CMD_USB 0x0000000400000000 /* USB Support */
#define CFG_CMD_DOC 0x0000000800000000 /* Disk-On-Chip Support */
#define CFG_CMD_JFFS2 0x0000001000000000 /* JFFS2 Support */
+#define CFG_CMD_DTT 0x0000002000000000 /* Digital Therm and Thermostat */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DOC | \
+ CFG_CMD_DTT | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Read Digital Thermometers & Thermostats
+ */
+#ifndef _CMD_DTT_H
+#define _CMD_DTT_H
+
+#if (CONFIG_COMMANDS & CFG_CMD_DTT)
+
+#define CMD_TBL_DTT MK_CMD_TBL_ENTRY( \
+ "dtt", 3, 1, 1, do_dtt, \
+ "dtt - Digital Thermometer and Themostat\n", \
+ " - Read temperature from digital thermometer and thermostat.\n" \
+),
+extern int do_dtt (cmd_tbl_t *, bd_t *, int, int, char *[]);
+
+#else
+
+#define CMD_TBL_DTT
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_DTT) */
+
+#endif /* _CMD_DTT_H */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
+#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_405 1 /* ...member of PPC405 family */
+#define CONFIG_4xx 1 /* ...member of PPC405 family */
#define CONFIG_BOARD_PRE_INIT 1 /* setup for 405gp */
#define CONFIG_SYS_CLK_FREQ 25000000 /* .. frequency in L1 */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
+#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define BCSR_ADDR ((uint) 0xFF010000)
#define BCSR_SIZE ((uint)(64 * 1024))
-#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
-
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */
#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
#else
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
#endif
/* BCSRx - Board Control and Status Registers */
#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \
& ~CFG_CMD_BSP \
& ~CFG_CMD_DOC \
+ & ~CFG_CMD_DTT \
& ~CFG_CMD_EEPROM \
& ~CFG_CMD_ELF \
& ~CFG_CMD_FDC \
* EEPROM of the SDRAM
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
-#define CONFIG_I2C405
#define CONFIG_I2C
#define CONFIG_I2C_X
#define CFG_I2C_EEPROM_ADDR 0x53
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
+ CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FDC | \
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* EEPROM of the SDRAM
* The Atmel EEPROM uses 16Bit addressing.
***************************************************************/
+#define CONFIG_I2C
#define CONFIG_I2C_X
-#define CONFIG_I2C405
#define CFG_I2C_EEPROM_ADDR 0x53
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */
+
/* The Atmel 24C128/256 has 64 byte page write mode using last 6 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_BITS 6
#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above val. */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
/*
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above val. */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
#endif
/*
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_DIMM_EEPROM 1 /* use dimm eeprom for setup */
+#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
/*
* Miscellaneous configurable options
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
~CFG_CMD_PCI & \
~CFG_CMD_PCMCIA & \
~CFG_CMD_SCSI & \
- ~CFG_CMD_USB )
+ ~CFG_CMD_USB & \
+ ~CFG_CMD_DTT )
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
CFG_CMD_PCMCIA | \
CFG_CMD_PCI | \
CFG_CMD_USB | \
- CFG_CMD_SCSI ) )
+ CFG_CMD_SCSI | \
+ CFG_CMD_DTT ) )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Digital Thermometers and Thermostats.
+ */
+#ifndef _DTT_H_
+#define _DTT_H_
+
+#if defined(CONFIG_DTT_LM75) || defined(CONFIG_DTT_DS1621)
+#define CONFIG_DTT /* We have a DTT */
+
+#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
+#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
+#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
+#ifndef CFG_DTT_MAX_TEMP
+#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
+#endif
+#ifndef CFG_DTT_HYSTERESIS
+#define CFG_DTT_HYSTERESIS 5 /* 5 C */
+#endif
+
+extern void dtt_init(void);
+extern int dtt_read(int sensor, int reg);
+extern int dtt_write(int sensor, int reg, int val);
+extern int dtt_get_temp(int sensor);
+#endif
+
+#if defined(CONFIG_DTT_LM75)
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_SET 0x3
+#endif
+
+#if defined(CONFIG_DTT_DS1621)
+#define DTT_READ_TEMP 0xAA
+#define DTT_READ_COUNTER 0xA8
+#define DTT_READ_SLOPE 0xA9
+#define DTT_WRITE_START_CONV 0xEE
+#define DTT_WRITE_STOP_CONV 0x22
+#define DTT_TEMP_HIGH 0xA1
+#define DTT_TEMP_LOW 0xA2
+#define DTT_CONFIG 0xAC
+#en
extern int parse_string_outer(char *s, int flag);
extern int parse_file_outer(void);
-#endif
\ No newline at end of file
+#endif
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
+#define CONFIG_I2C_4XX /* 4xx I2C variant */
+
void i2c_init(void);
int i2c_receive(unsigned char address,
unsigned short size_to_expect, unsigned char datain[] );
int i2c_send(unsigned char address,
unsigned short size_to_send, unsigned char dataout[] );
-int i2c_write_page(uchar *addr, int alen, uchar *data, int dlen, int dsize);
+int i2c_wr_page(uchar *addr, int alen, uchar *data, int dlen, int dsize);
#endif
#if !defined(CONFIG_MPC824X) && !defined(CONFIG_4xx) && !defined(CONFIG_IOP480)/* !( CONFIG_4xx || CONFIG_IOP480) */
#endif /* _ASMLANGUAGE */
+#define RESET_VECTOR 0xfffffffc
+#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+ line aligned data. */
+
#endif /* __PPC4XX_H__ */
+
read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); // read burst
if (bbclk.CH) {
- printf("ds1302: rtc_get: Clock was halted, clock probably
- corrupt\n");
+ printf("ds1302: rtc_get: Clock was halted, clock probably "
+ "corrupt\n");
}
tmp->tm_sec=10*bbclk.sec10+bbclk.sec;
-e s/Power\ Macintosh/ppc/ \
-e s/macppc/ppc/)
-HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/')
+HOSTOS := $(shell uname -s | tr A-Z a-z | \
+ sed -e 's/\(cygwin\).*/cygwin/')
TOOLSUBDIRS =
projects / users / rw / ppcboot.git / commitdiff