unsigned int val;
        int ret, count;
 
-       ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
-                                ADSP2_SYS_ENA, ADSP2_SYS_ENA);
+       ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
+                                      ADSP2_SYS_ENA, ADSP2_SYS_ENA);
        if (ret != 0)
                return ret;
 
                val = (val & ARIZONA_SYSCLK_FREQ_MASK)
                        >> ARIZONA_SYSCLK_FREQ_SHIFT;
 
-               ret = regmap_update_bits(dsp->regmap,
-                                        dsp->base + ADSP2_CLOCKING,
-                                        ADSP2_CLK_SEL_MASK, val);
+               ret = regmap_update_bits_async(dsp->regmap,
+                                              dsp->base + ADSP2_CLOCKING,
+                                              ADSP2_CLK_SEL_MASK, val);
                if (ret != 0) {
                        adsp_err(dsp, "Failed to set clock rate: %d\n",
                                 ret);
                if (ret != 0)
                        goto err;
 
-               ret = regmap_update_bits(dsp->regmap,
-                                        dsp->base + ADSP2_CONTROL,
-                                        ADSP2_CORE_ENA | ADSP2_START,
-                                        ADSP2_CORE_ENA | ADSP2_START);
+               ret = regmap_update_bits_async(dsp->regmap,
+                                              dsp->base + ADSP2_CONTROL,
+                                              ADSP2_CORE_ENA | ADSP2_START,
+                                              ADSP2_CORE_ENA | ADSP2_START);
                if (ret != 0)
                        goto err;