riscv: hwprobe: export Zacas ISA extension

Export Zacas ISA extension through hwprobe.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231220155723.684081-6-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 10bd7b170118e8e6df83746ff9fcbab2329f9793..bff68004ad43d2b69a94c74a96d1d107fee030b3 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -165,6 +165,10 @@ The following keys are defined:
        defined in the RISC-V ISA manual starting from commit 5618fb5a216b
        ("Ztso is now ratified.")
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
+       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
+       from commit 5059e0ca641c ("update to ratified").
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 01ac3dc196e5201f31727a42c01a195c24e9fbb1..ac65bb43c8e723f8b226ff25c737845208cac086 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -57,6 +57,7 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZVFHMIN       (1 << 31)
 #define                RISCV_HWPROBE_EXT_ZFA           (1ULL << 32)
 #define                RISCV_HWPROBE_EXT_ZTSO          (1ULL << 33)
+#define                RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)

diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 6564fa9e7a7ff9ce38f93a5f8f7fb8fbc52ffcda..6c680c75ac0d44e48b6917afc8d615a73d35471a 100644 (file)
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -175,6 +175,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZKT);
                EXT_KEY(ZIHINTNTL);
                EXT_KEY(ZTSO);
+               EXT_KEY(ZACAS);
 
                if (has_vector()) {
                        EXT_KEY(ZVBB);