clk: zynq: pll: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index e5f8fb704df24e9c6e87854ce2c43fb86fa98cd3..5eca1c14981aceb95801cd000c6c7b30b9830696 100644 (file)
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -48,18 +48,20 @@ struct zynq_pll {
  * @prate:     Clock frequency of parent clock
  * Return:     frequency closest to @rate the hardware can generate.
  */
-static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *prate)
+static int zynq_pll_determine_rate(struct clk_hw *hw,
+                                  struct clk_rate_request *req)
 {
        u32 fbdiv;
 
-       fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+       fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate);
        if (fbdiv < PLL_FBDIV_MIN)
                fbdiv = PLL_FBDIV_MIN;
        else if (fbdiv > PLL_FBDIV_MAX)
                fbdiv = PLL_FBDIV_MAX;
 
-       return *prate * fbdiv;
+       req->rate = req->best_parent_rate * fbdiv;
+
+       return 0;
 }
 
 /**
@@ -167,7 +169,7 @@ static const struct clk_ops zynq_pll_ops = {
        .enable = zynq_pll_enable,
        .disable = zynq_pll_disable,
        .is_enabled = zynq_pll_is_enabled,
-       .round_rate = zynq_pll_round_rate,
+       .determine_rate = zynq_pll_determine_rate,
        .recalc_rate = zynq_pll_recalc_rate
 };