We need a bit more flexibility here in the future, bits get shuffled
around.
v2: more descriptive commit message (Jani Nikula)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
        }
 
        while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
-               u32 send_ctl = i9xx_get_aux_send_ctl(intel_dp,
-                                                    has_aux_irq,
-                                                    send_bytes,
-                                                    aux_clock_divider);
+               u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
+                                                         has_aux_irq,
+                                                         send_bytes,
+                                                         aux_clock_divider);
 
                /* Must try at least 3 times according to DP spec */
                for (try = 0; try < 5; try++) {
        else
                intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
 
+       intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
+
        /* Preserve the current hw state. */
        intel_dp->DP = I915_READ(intel_dp->output_reg);
        intel_dp->attached_connector = intel_connector;
 
        struct intel_connector *attached_connector;
 
        uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
+       /*
+        * This function returns the value we have to program the AUX_CTL
+        * register with to kick off an AUX transaction.
+        */
+       uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
+                                    bool has_aux_irq,
+                                    int send_bytes,
+                                    uint32_t aux_clock_divider);
 };
 
 struct intel_digital_port {