.end            = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
                .flags          = IORESOURCE_MEM,
        },
+       { /* DSP L2 RAM */
+               .name           = "l2sram",
+               .start          = DA8XX_DSP_L2_RAM_BASE,
+               .end            = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
+               .flags          = IORESOURCE_MEM,
+       },
+       { /* DSP L1P RAM */
+               .name           = "l1pram",
+               .start          = DA8XX_DSP_L1P_RAM_BASE,
+               .end            = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
+               .flags          = IORESOURCE_MEM,
+       },
+       { /* DSP L1D RAM */
+               .name           = "l1dram",
+               .start          = DA8XX_DSP_L1D_RAM_BASE,
+               .end            = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
+               .flags          = IORESOURCE_MEM,
+       },
        { /* dsp irq */
                .start          = IRQ_DA8XX_CHIPINT0,
                .end            = IRQ_DA8XX_CHIPINT0,
 
 #define DA8XX_VPIF_BASE                0x01e17000
 #define DA8XX_GPIO_BASE                0x01e26000
 #define DA8XX_PSC1_BASE                0x01e27000
+
+#define DA8XX_DSP_L2_RAM_BASE  0x11800000
+#define DA8XX_DSP_L1P_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x600000)
+#define DA8XX_DSP_L1D_RAM_BASE (DA8XX_DSP_L2_RAM_BASE + 0x700000)
+
 #define DA8XX_AEMIF_CS2_BASE   0x60000000
 #define DA8XX_AEMIF_CS3_BASE   0x62000000
 #define DA8XX_AEMIF_CTL_BASE   0x68000000