drm/amd/display: Remove redundant null checks

The null checks are redundant as they were already dereferenced
previously, as reported by Coverity; therefore the null checks
are removed.

This fixes 7 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ee4b02c8c80788f1f72f27f8f96c8bad88331131..06f0c41ad6f1a26b301ef3f8209d84e8441df738 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -553,7 +553,7 @@ static void dcn32_auto_dpm_test_log(
        //
        //                              AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
        ////////////////////////////////////////////////////////////////////////////
-       if (new_clocks && active_pipe_count > 0 &&
+       if (active_pipe_count > 0 &&
                new_clocks->dramclk_khz > 0 &&
                new_clocks->fclk_khz > 0 &&
                new_clocks->dcfclk_khz > 0 &&

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fce1c3e0309498de9f979190f8f598941a2601d8..a4ba6f99cd34a50e62c48c583b4bc694876162d8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2640,7 +2640,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
 
                if (u->plane_info)
                        format = u->plane_info->format;
-               else if (u->surface)
+               else
                        format = u->surface->format;
 
                if (dce_use_lut(format))
@@ -2741,7 +2741,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
                if (stream_update->mst_bw_update)
                        su_flags->bits.mst_bw = 1;
 
-               if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
+               if (stream_update->stream->freesync_on_desktop &&
                        (stream_update->vrr_infopacket || stream_update->allow_freesync ||
                                stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
                        su_flags->bits.fams_changed = 1;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1cba8f58f1e61ebd73797231d03cac73d28ac50b..eb053e1791c076c722625e6448a20c466b8003a4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2099,7 +2099,7 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
                        timing->h_border_right;
        width = h_active / count;
 
-       if (otg_master->stream_res.tg && otg_master->stream)
+       if (otg_master->stream_res.tg)
                two_pixel_alignment_required =
                                otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
                                /*

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
index a7d02da16bb593a6fd372c2731e0f451ed8a5703..d5ead0205053b24d21de4dde1b06b6c4bfb70064 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
@@ -102,9 +102,7 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in
        struct dml2_soc_state_table *dml_clk_table = &dml_soc_bb->clk_table;
 
        /* override clocks if smu is present */
-       if (in_dc->clk_mgr &&
-                       in_dc->clk_mgr->funcs->is_smu_present &&
-                       in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
+       if (in_dc->clk_mgr->funcs->is_smu_present && in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
                /* dcfclk */
                if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
                        dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index f489371a3bc6b0d25f53a5f81be537a2a3ba34ac..1b410aff6c565fa68820b3a1eb7632a98e2135af 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -742,12 +742,10 @@ void dce110_edp_wait_for_hpd_ready(
                return;
        }
 
-       if (link != NULL) {
-               if (link->panel_config.pps.extra_t3_ms > 0) {
-                       int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
+       if (link->panel_config.pps.extra_t3_ms > 0) {
+               int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
 
-                       msleep(extra_t3_in_ms);
-               }
+               msleep(extra_t3_in_ms);
        }
 
        dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index aaeeb0ff4d849e61bd499e7da84907781df7623b..bdbb4a71651fa8eafdd5c1b2ba90480bb3fbfe7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -271,58 +271,55 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
        }
 
        if (enable) {
-               if (dc->current_state) {
+               /* 1. Check no memory request case for CAB.
+                * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
+                */
+               if (dcn32_check_no_memory_request_for_cab(dc)) {
+                       /* Enable no-memory-requests case */
+                       memset(&cmd, 0, sizeof(cmd));
+                       cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+                       cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
+                       cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 
-                       /* 1. Check no memory request case for CAB.
-                        * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
-                        */
-                       if (dcn32_check_no_memory_request_for_cab(dc)) {
-                               /* Enable no-memory-requests case */
-                               memset(&cmd, 0, sizeof(cmd));
-                               cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
-                               cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
-                               cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+                       dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 
-                               dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
+                       return true;
+               }
 
-                               return true;
-                       }
+               /* 2. Check if all surfaces can fit in CAB.
+                * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
+                * and configure HUBP's to fetch from MALL
+                */
+               ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
 
-                       /* 2. Check if all surfaces can fit in CAB.
-                        * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
-                        * and configure HUBP's to fetch from MALL
-                        */
-                       ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
+               /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
+                * or TMZ surface, don't try to enter MALL.
+                */
+               for (i = 0; i < dc->current_state->stream_count; i++) {
+                       for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
+                               plane = dc->current_state->stream_status[i].plane_states[j];
 
-                       /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
-                        * or TMZ surface, don't try to enter MALL.
-                        */
-                       for (i = 0; i < dc->current_state->stream_count; i++) {
-                               for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
-                                       plane = dc->current_state->stream_status[i].plane_states[j];
-
-                                       if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
-                                                       plane->address.tmz_surface) {
-                                               mall_ss_unsupported = true;
-                                               break;
-                                       }
-                               }
-                               if (mall_ss_unsupported)
+                               if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
+                                               plane->address.tmz_surface) {
+                                       mall_ss_unsupported = true;
                                        break;
+                               }
                        }
-                       if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
-                               memset(&cmd, 0, sizeof(cmd));
-                               cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
-                               cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
-                               cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
-                               cmd.cab.cab_alloc_ways = (uint8_t)ways;
-
-                               dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
+                       if (mall_ss_unsupported)
+                               break;
+               }
+               if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
+                       memset(&cmd, 0, sizeof(cmd));
+                       cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
+                       cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
+                       cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
+                       cmd.cab.cab_alloc_ways = (uint8_t)ways;
 
-                               return true;
-                       }
+                       dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 
+                       return true;
                }
+
                return false;
        }