CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
 
                /* See if we got it */
-               ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
-                               CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
-                               CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
-                               IWL_EEPROM_SEM_TIMEOUT);
+               ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
+                                   CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
+                                   IWL_EEPROM_SEM_TIMEOUT);
                if (ret >= 0) {
                        IWL_DEBUG_EEPROM(trans->dev,
                                         "Acquired semaphore after %d tries.\n",
 
        iwl_write32(trans, CSR_EEPROM_REG,
                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
-       ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
-                                CSR_EEPROM_REG_READ_VALID_MSK,
-                                CSR_EEPROM_REG_READ_VALID_MSK,
-                                IWL_EEPROM_ACCESS_TIMEOUT);
+       ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
+                           CSR_EEPROM_REG_READ_VALID_MSK,
+                           IWL_EEPROM_ACCESS_TIMEOUT);
        if (ret < 0) {
                IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
                return ret;
                        iwl_write32(trans, CSR_EEPROM_REG,
                                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 
-                       ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
-                                          CSR_EEPROM_REG_READ_VALID_MSK,
-                                          CSR_EEPROM_REG_READ_VALID_MSK,
-                                          IWL_EEPROM_ACCESS_TIMEOUT);
+                       ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
+                                           CSR_EEPROM_REG_READ_VALID_MSK,
+                                           IWL_EEPROM_ACCESS_TIMEOUT);
                        if (ret < 0) {
                                IWL_ERR(trans,
                                        "Time out reading EEPROM[%d]\n", addr);
 
 
 #define IWL_POLL_INTERVAL 10   /* microseconds */
 
-int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
-                u32 bits, u32 mask, int timeout)
+int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
+                      u32 bits, u32 mask, int timeout)
 {
        int t = 0;
 
 
        return -ETIMEDOUT;
 }
-IWL_EXPORT_SYMBOL(iwl_poll_bit);
+IWL_EXPORT_SYMBOL(iwl_poll_bits_mask);
 
 u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
 {
         * device-internal resources is supported, e.g. iwl_write_prph()
         * and accesses to uCode SRAM.
         */
-       err = iwl_poll_bit(trans, CSR_GP_CNTRL, poll_ready, poll_ready, 25000);
+       err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);
        if (err < 0) {
                IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
 
 
        iwl_trans_set_bits_mask(trans, reg, mask, 0);
 }
 
-int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
-                u32 bits, u32 mask, int timeout);
+int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
+                      u32 bits, u32 mask, int timeout);
+static inline int iwl_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,
+                               int timeout)
+{
+       return iwl_poll_bits_mask(trans, addr, bits, bits, timeout);
+}
 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
                        int timeout);
 
 
                iwl_set_bit(trans, CSR_GP_CNTRL,
                            CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
 
-               ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
-                                  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
-                                  CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
-                                  100);
+               ret = iwl_poll_bits(trans, CSR_GP_CNTRL,
+                                   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
+                                   100);
                usleep_range(10000, 20000);
        } else {
                iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 
-               ret = iwl_poll_bit(trans, CSR_RESET,
-                                  CSR_RESET_REG_FLAG_MASTER_DISABLED,
-                                  CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
+               ret = iwl_poll_bits(trans, CSR_RESET,
+                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
        }
 
        if (ret < 0)
                    CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
 
        /* See if we got it */
-       ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
-                          CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
-                          CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
-                          HW_READY_TIMEOUT);
+       ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
+                           CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
+                           HW_READY_TIMEOUT);
 
        if (ret >= 0)
                iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
         * 5000 series and later (including 1000 series) have non-volatile SRAM,
         * and do not save/restore SRAM when power cycling.
         */
-       ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
+       ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);
        if (unlikely(ret < 0)) {
                u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
 
 
        }
 
        /* Wait for DMA channels to be idle */
-       ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
+       ret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);
        if (ret < 0)
                IWL_ERR(trans,
                        "Failing on timeout while stopping DMA channel %d [0x%08x]\n",