spin_lock_irqsave(&kiq->ring_lock, flags);
 
-       if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
+       if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {
                spin_unlock_irqrestore(&kiq->ring_lock, flags);
                return -ENOMEM;
        }
                               0, 1, 0x20);
        gfx_v10_0_ring_emit_reg_wait(kiq_ring,
                                     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
-       kiq->pmf->kiq_map_queues(kiq_ring, ring);
        amdgpu_ring_commit(kiq_ring);
-
-       spin_unlock_irqrestore(&kiq->ring_lock, flags);
-
        r = amdgpu_ring_test_ring(kiq_ring);
+       spin_unlock_irqrestore(&kiq->ring_lock, flags);
        if (r)
                return r;
 
                return r;
        }
 
+       spin_lock_irqsave(&kiq->ring_lock, flags);
+
+       if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
+               spin_unlock_irqrestore(&kiq->ring_lock, flags);
+               return -ENOMEM;
+       }
+       kiq->pmf->kiq_map_queues(kiq_ring, ring);
+       amdgpu_ring_commit(kiq_ring);
+       r = amdgpu_ring_test_ring(kiq_ring);
+       spin_unlock_irqrestore(&kiq->ring_lock, flags);
+       if (r)
+               return r;
+
        r = amdgpu_ring_test_ring(ring);
        if (r)
                return r;