PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
 
-static void i915_pineview_get_mem_freq(struct drm_device *dev)
+static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        u32 tmp;
 
        tmp = I915_READ(CLKCFG);
        dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 }
 
-static void i915_ironlake_get_mem_freq(struct drm_device *dev)
+static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
        u16 ddrpll, csipll;
 
        ddrpll = I915_READ16(DDRMPLL1);
 
        /* For cxsr */
        if (IS_PINEVIEW(dev_priv))
-               i915_pineview_get_mem_freq(dev);
+               i915_pineview_get_mem_freq(dev_priv);
        else if (IS_GEN5(dev_priv))
-               i915_ironlake_get_mem_freq(dev);
+               i915_ironlake_get_mem_freq(dev_priv);
 
        /* For FIFO watermark updates */
        if (INTEL_INFO(dev)->gen >= 9) {