ARM: tegra: clock: Don't BUG on changing an enabled PLL

When updating the CPU PLL frequency, keeping the PLL enabled avoids
ramping the PLL all the way down and back up again.  Remove the BUG_ON
in tegra2_pll_clk_set_rate to allow the rate to change while the PLL
is enabled.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 6442abe0120d2b15b797fc23ac0e8334a8612064..600a5a473ab509011c9adba7b06b1f0d62e0c268 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -620,7 +620,6 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
        const struct clk_pll_table *sel;
 
        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-       BUG_ON(c->refcnt != 0);
 
        input_rate = c->parent->rate;
        for (sel = c->pll_table; sel->input_rate != 0; sel++) {