target/xtensa: add internal/noop SRs and opcodes

Add two special registers: MMID and DDR:
- MMID is write-only and the only side effect of writing to it is output
  to the trace port, which is not emulated;
- DDR is only accessible in debug mode, which is not emulated.

Add two debug-mode-only opcodes:
- rfdd and rfdo do return from the debug mode, which is not emulated.

Add three internal opcodes for full MMU:
- hwwdtlba and hwwitlba are the internal opcodes that write a value into
  autoupdate DTLB or ITLB entry.
- ldpte is internal opcode that loads PTE entry that covers the most
  recent page fault address.
None of these three opcodes may appear in a valid instruction.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index e93bbb3c6d1e03e424616e6c96a9c9d61f8fdf3b..80e9b47e84e914978bc64946fb6653b6a78de9c9 100644 (file)
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -127,6 +127,7 @@ enum {
     WINDOW_BASE = 72,
     WINDOW_START = 73,
     PTEVADDR = 83,
+    MMID = 89,
     RASID = 90,
     ITLBCFG = 91,
     DTLBCFG = 92,
@@ -134,6 +135,7 @@ enum {
     MEMCTL = 97,
     CACHEATTR = 98,
     ATOMCTL = 99,
+    DDR = 104,
     IBREAKA = 128,
     DBREAKA = 144,
     DBREAKC = 160,

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 27078e9f5ba7b19d55b76576ad904a9676c5d503..3e8a0015b31470e52933b536f8d9b552fb73d8b7 100644 (file)
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -135,6 +135,7 @@ static const XtensaReg sregnames[256] = {
     [WINDOW_START] = XTENSA_REG("WINDOW_START",
             XTENSA_OPTION_WINDOWED_REGISTER),
     [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
+    [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL),
     [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
     [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
     [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
@@ -142,6 +143,7 @@ static const XtensaReg sregnames[256] = {
     [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL),
     [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
     [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
+    [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG),
     [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
     [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
     [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
@@ -2761,6 +2763,12 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "extw",
         .translate = translate_nop,
+    }, {
+        .name = "hwwdtlba",
+        .translate = translate_ill,
+    }, {
+        .name = "hwwitlba",
+        .translate = translate_ill,
     }, {
         .name = "idtlb",
         .translate = translate_itlb,
@@ -2846,6 +2854,9 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "ldinc",
         .translate = translate_mac16,
         .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
+    }, {
+        .name = "ldpte",
+        .translate = translate_ill,
     }, {
         .name = "loop",
         .translate = translate_loop,
@@ -3264,9 +3275,15 @@ static const XtensaOpcodeOps core_ops[] = {
     }, {
         .name = "retw.n",
         .translate = translate_retw,
+    }, {
+        .name = "rfdd",
+        .translate = translate_ill,
     }, {
         .name = "rfde",
         .translate = translate_rfde,
+    }, {
+        .name = "rfdo",
+        .translate = translate_ill,
     }, {
         .name = "rfe",
         .translate = translate_rfe,
@@ -3367,6 +3384,10 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "rsr.dbreakc1",
         .translate = translate_rsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+    }, {
+        .name = "rsr.ddr",
+        .translate = translate_rsr,
+        .par = (const uint32_t[]){DDR},
     }, {
         .name = "rsr.debugcause",
         .translate = translate_rsr,
@@ -3802,6 +3823,10 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "wsr.dbreakc1",
         .translate = translate_wsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+    }, {
+        .name = "wsr.ddr",
+        .translate = translate_wsr,
+        .par = (const uint32_t[]){DDR},
     }, {
         .name = "wsr.debugcause",
         .translate = translate_wsr,
@@ -3994,6 +4019,10 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "wsr.misc3",
         .translate = translate_wsr,
         .par = (const uint32_t[]){MISC + 3},
+    }, {
+        .name = "wsr.mmid",
+        .translate = translate_wsr,
+        .par = (const uint32_t[]){MMID},
     }, {
         .name = "wsr.prid",
         .translate = translate_wsr,
@@ -4121,6 +4150,10 @@ static const XtensaOpcodeOps core_ops[] = {
         .name = "xsr.dbreakc1",
         .translate = translate_xsr,
         .par = (const uint32_t[]){DBREAKC + 1},
+    }, {
+        .name = "xsr.ddr",
+        .translate = translate_xsr,
+        .par = (const uint32_t[]){DDR},
     }, {
         .name = "xsr.debugcause",
         .translate = translate_xsr,