drm/amdgpu: add error address query for umc ras

umc error address query can get ce/ue error address and clear error
status

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e15fedb0ce7340df68c220833c5f727cc19ecfa1..2a4878646b732d3a77cbd8b5999dfc04c412c24e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -601,6 +601,11 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
        case AMDGPU_RAS_BLOCK__UMC:
                if (adev->umc.funcs->query_ras_error_count)
                        adev->umc.funcs->query_ras_error_count(adev, &err_data);
+               /* umc query_ras_error_address is also responsible for clearing
+                * error status
+                */
+               if (adev->umc.funcs->query_ras_error_address)
+                       adev->umc.funcs->query_ras_error_address(adev, &err_data);
                break;
        case AMDGPU_RAS_BLOCK__GFX:
                if (adev->gfx.funcs->query_ras_error_count)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 24387026fdeebe61efbb281caec2cdd99d39291a..c7647c6988dffa94b1ce63c3f62d8bcbf52548c2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -249,6 +249,11 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
        kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
        if (adev->umc.funcs->query_ras_error_count)
                adev->umc.funcs->query_ras_error_count(adev, err_data);
+       /* umc query_ras_error_address is also responsible for clearing
+        * error status
+        */
+       if (adev->umc.funcs->query_ras_error_address)
+               adev->umc.funcs->query_ras_error_address(adev, err_data);
        amdgpu_ras_reset_gpu(adev, 0);
        return AMDGPU_RAS_UE;
 }