]> www.infradead.org Git - users/hch/misc.git/commitdiff
drm/amdgpu: fix UVD contiguous CS mapping problem
authorChristian König <christian.koenig@amd.com>
Fri, 29 Nov 2024 13:19:21 +0000 (14:19 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 5 Dec 2024 19:14:53 +0000 (14:14 -0500)
When starting the mpv player, Radeon R9 users are observing
the below error in dmesg.

[drm:amdgpu_uvd_cs_pass2 [amdgpu]]
*ERROR* msg/fb buffer ff00f7c000-ff00f7e000 out of 256MB segment!

The patch tries to set the TTM_PL_FLAG_CONTIGUOUS for both user
flag(AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) set and not set cases.

v2: Make the TTM_PL_FLAG_CONTIGUOUS mandatory for user BO's.
v3: revert back to v1, but fix the check instead (chk).

Closes:https://gitlab.freedesktop.org/drm/amd/-/issues/3599
Closes:https://gitlab.freedesktop.org/drm/amd/-/issues/3501
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.10+
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

index d891ab779ca7f5168f8fd4e80c4f100c9b643186..5df21529b3b13e26a68c2526d1830cef0d15f8ad 100644 (file)
@@ -1801,13 +1801,18 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
        if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)
                return -EINVAL;
 
+       /* Make sure VRAM is allocated contigiously */
        (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-       amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
-       for (i = 0; i < (*bo)->placement.num_placement; i++)
-               (*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
-       r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
-       if (r)
-               return r;
+       if ((*bo)->tbo.resource->mem_type == TTM_PL_VRAM &&
+           !((*bo)->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {
+
+               amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
+               for (i = 0; i < (*bo)->placement.num_placement; i++)
+                       (*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
+               r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
+               if (r)
+                       return r;
+       }
 
        return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
 }
index 31fd30dcd593bad8ed0f092314720591fc5fa1be..65bb26215e867a9841e73c1bbb711adf33f4c379 100644 (file)
@@ -551,6 +551,8 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
        for (i = 0; i < abo->placement.num_placement; ++i) {
                abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
                abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
+               if (abo->placements[i].mem_type == TTM_PL_VRAM)
+                       abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
        }
 }