Can cause hangs when enabled in certain motherboards.
Set radeon.aspm=0 to disable aspm.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
         */
        bool fusion_platform = false;
 
+       if (radeon_aspm == 0)
+               return;
+
        if (!(rdev->flags & RADEON_IS_PCIE))
                return;
 
 
 extern int radeon_lockup_timeout;
 extern int radeon_fastfb;
 extern int radeon_dpm;
+extern int radeon_aspm;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 
 int radeon_lockup_timeout = 10000;
 int radeon_fastfb = 0;
 int radeon_dpm = -1;
+int radeon_aspm = -1;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(dpm, radeon_dpm, int, 0444);
 
+MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
+module_param_named(aspm, radeon_aspm, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
        radeon_PCI_IDS
 };
 
 {
        r600_enable_acpi_pm(rdev);
 
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
-               rv6xx_enable_l0s(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
-               rv6xx_enable_l1(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
-               rv6xx_enable_pll_sleep_in_l1(rdev);
+       if (radeon_aspm != 0) {
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
+                       rv6xx_enable_l0s(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
+                       rv6xx_enable_l1(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
+                       rv6xx_enable_pll_sleep_in_l1(rdev);
+       }
 }
 
 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
 
 
        rv770_enable_acpi_pm(rdev);
 
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
-               rv770_enable_l0s(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
-               rv770_enable_l1(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
-               rv770_enable_pll_sleep_in_l1(rdev);
+       if (radeon_aspm != 0) {
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
+                       rv770_enable_l0s(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
+                       rv770_enable_l1(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
+                       rv770_enable_pll_sleep_in_l1(rdev);
+       }
 }
 
 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev)
 
        bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
        bool disable_clkreq = false;
 
+       if (radeon_aspm == 0)
+               return;
+
        if (!(rdev->flags & RADEON_IS_PCIE))
                return;