RAS/AMD/ATL: Read DRAM hole base early

Read DRAM hole base when constructing the address map as the value will
not change during run time.

Signed-off-by: John Allen <john.allen@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Link: https://lore.kernel.org/r/20240606203313.51197-3-john.allen@amd.com

diff --git a/drivers/ras/amd/atl/core.c b/drivers/ras/amd/atl/core.c
index 7be4982fdf190091c3f4081780555ebfb7908de8..82f77f129d541903e7f05dfb9aba0772db0718cb 100644 (file)
--- a/drivers/ras/amd/atl/core.c
+++ b/drivers/ras/amd/atl/core.c
@@ -51,22 +51,11 @@ static bool legacy_hole_en(struct addr_ctx *ctx)
 
 static int add_legacy_hole(struct addr_ctx *ctx)
 {
-       u32 dram_hole_base;
-       u8 func = 0;
-
        if (!legacy_hole_en(ctx))
                return 0;
 
-       if (df_cfg.rev >= DF4)
-               func = 7;
-
-       if (df_indirect_read_broadcast(ctx->node_id, func, 0x104, &dram_hole_base))
-               return -EINVAL;
-
-       dram_hole_base &= DF_DRAM_HOLE_BASE_MASK;
-
-       if (ctx->ret_addr >= dram_hole_base)
-               ctx->ret_addr += (BIT_ULL(32) - dram_hole_base);
+       if (ctx->ret_addr >= df_cfg.dram_hole_base)
+               ctx->ret_addr += (BIT_ULL(32) - df_cfg.dram_hole_base);
 
        return 0;
 }
@@ -125,6 +114,9 @@ unsigned long norm_to_sys_addr(u8 socket_id, u8 die_id, u8 coh_st_inst_id, unsig
        ctx.inputs.die_id = die_id;
        ctx.inputs.coh_st_inst_id = coh_st_inst_id;
 
+       if (legacy_hole_en(&ctx) && !df_cfg.dram_hole_base)
+               return -EINVAL;
+
        if (determine_node_id(&ctx, socket_id, die_id))
                return -EINVAL;
 

diff --git a/drivers/ras/amd/atl/internal.h b/drivers/ras/amd/atl/internal.h
index cb0f96040fbd8327662214fc84ea64a9ba1ee737..3596ad5ca3e0b9a134ccf0d899898987d2dbd23d 100644 (file)
--- a/drivers/ras/amd/atl/internal.h
+++ b/drivers/ras/amd/atl/internal.h
@@ -135,6 +135,8 @@ struct df_config {
        /* Number of DRAM Address maps visible in a Coherent Station. */
        u8 num_coh_st_maps;
 
+       u32 dram_hole_base;
+
        /* Global flags to handle special cases. */
        struct df_flags flags;
 };

diff --git a/drivers/ras/amd/atl/system.c b/drivers/ras/amd/atl/system.c
index 248ea493b841456727a2c49ca3620e432050fd3b..8423c9f3a8d264d0d9514e0b41f2e182fa19ff41 100644 (file)
--- a/drivers/ras/amd/atl/system.c
+++ b/drivers/ras/amd/atl/system.c
@@ -223,6 +223,21 @@ static int determine_df_rev(void)
        return -EINVAL;
 }
 
+static int get_dram_hole_base(void)
+{
+       u8 func = 0;
+
+       if (df_cfg.rev >= DF4)
+               func = 7;
+
+       if (df_indirect_read_broadcast(0, func, 0x104, &df_cfg.dram_hole_base))
+               return -EINVAL;
+
+       df_cfg.dram_hole_base &= DF_DRAM_HOLE_BASE_MASK;
+
+       return 0;
+}
+
 static void get_num_maps(void)
 {
        switch (df_cfg.rev) {
@@ -266,6 +281,7 @@ static void dump_df_cfg(void)
 
        pr_debug("num_coh_st_maps=%u",                  df_cfg.num_coh_st_maps);
 
+       pr_debug("dram_hole_base=0x%x",                 df_cfg.dram_hole_base);
        pr_debug("flags.legacy_ficaa=%u",               df_cfg.flags.legacy_ficaa);
        pr_debug("flags.socket_id_shift_quirk=%u",      df_cfg.flags.socket_id_shift_quirk);
 }
@@ -282,6 +298,9 @@ int get_df_system_info(void)
 
        get_num_maps();
 
+       if (get_dram_hole_base())
+               pr_warn("Failed to read DRAM hole base");
+
        dump_df_cfg();
 
        return 0;