]> www.infradead.org Git - users/hch/dma-mapping.git/commitdiff
drm/amdgpu/gfx10: associate mes queue id with fence v2
authorJack Xiao <Jack.Xiao@amd.com>
Fri, 20 Mar 2020 04:03:08 +0000 (12:03 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:03:45 +0000 (10:03 -0400)
Associate mes queue id with fence, so that EOP trap handler can look up
which queue has issued the fence.

v2: move mes queue flag to amdgpu_mes_ctx.h

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index f3e1ba1a889f1eb9132a305eaa749a65ff43d9ee..544f1aa86edf935e52b796e5bdde5485e8f49d40 100644 (file)
@@ -115,4 +115,6 @@ struct amdgpu_mes_ctx_data {
 #define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
 #define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
 
+#define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
+
 #endif
index d06807355f5f91cfea6250b4fec901d67e059ed9..e6e6012960972a5f3471a91a5d6ecc3426394d38 100644 (file)
@@ -8678,7 +8678,8 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
        amdgpu_ring_write(ring, upper_32_bits(addr));
        amdgpu_ring_write(ring, lower_32_bits(seq));
        amdgpu_ring_write(ring, upper_32_bits(seq));
-       amdgpu_ring_write(ring, 0);
+       amdgpu_ring_write(ring, ring->is_mes_queue ?
+                        (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
 }
 
 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)