arm64: dts: rockchip: Add HDMI0 PHY to rk3588

Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 36b1b7acfe6a15042600a595875054744d48f257..3a15a30543c3bfbe8bfd90df4341848b48b84689 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -586,6 +586,11 @@
                };
        };
 
+       hdptxphy0_grf: syscon@fd5e0000 {
+               compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+               reg = <0x0 0xfd5e0000 0x0 0x100>;
+       };
+
        ioc: syscon@fd5f0000 {
                compatible = "rockchip,rk3588-ioc", "syscon";
                reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -2360,6 +2365,22 @@
                #dma-cells = <1>;
        };
 
+       hdptxphy_hdmi0: phy@fed60000 {
+               compatible = "rockchip,rk3588-hdptx-phy";
+               reg = <0x0 0xfed60000 0x0 0x2000>;
+               clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+               clock-names = "ref", "apb";
+               #phy-cells = <0>;
+               resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+                        <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+                        <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+                        <&cru SRST_HDPTX0_LCPLL>;
+               reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+                             "lcpll";
+               rockchip,grf = <&hdptxphy0_grf>;
+               status = "disabled";
+       };
+
        combphy0_ps: phy@fee00000 {
                compatible = "rockchip,rk3588-naneng-combphy";
                reg = <0x0 0xfee00000 0x0 0x100>;