* Patch by Stefan Roese, 17 Jun 2002:

  - 405gp_enet.c: MAL error debug printf 'M' removed (rx de interrupt
    may occur upon many incoming packets with only 4 rx buffers).

* Patch by Yamazaki, 09 May 2002:
  Fix EPIC problems on Sandpoint 8245 boards

* Patch by Jerry Van Baren, 19 Jun 2002:
  Fix I2C on Sandpoint 8240 board

diff --git a/CHANGELOG b/CHANGELOG
index 6cb90ec541188ba2089425932c8d2d4936470ed0..121677ca01f482c9e35af167fd3f62b13e574fa3 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,19 +1,17 @@
-
-       B I G   F A T   W A R N I N G :
-       ===============================
-
-        We are working on the Grand Unifying I2C interface patch. The
-        current version of PPCBoot may not run, and even corrupt your
-        EEPROM contents. Use at your own risk!
-
-       You have been warned!
-
-       If you want to play safe, use version 1.1.5!
-
 ======================================================================
 Modifications for 1.1.6:
 ======================================================================
 
+* Patch by Stefan Roese, 17 Jun 2002:
+  - 405gp_enet.c: MAL error debug printf 'M' removed (rx de interrupt
+    may occur upon many incoming packets with only 4 rx buffers).
+
+* Patch by Yamazaki, 09 May 2002:
+  Fix EPIC problems on Sandpoint 8245 boards
+
+* Patch by Jerry Van Baren, 19 Jun 2002:
+  Fix I2C on Sandpoint 8240 board
+
 * Patch by Stefan Roese, 13 Jun 2002:
   - PPC405GPr support completed: To support this and all other 16kB
     DCache 405 ppc's, make sure to set CFG_DCACHE_SIZE to 16kB in

diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c
index 22adbeeb569b0f435963bab7d20091f49c02433a..c4f5019a3035ada6bdf51711e6e5fe9a869e9760 100644 (file)
--- a/board/lwmon/flash.c
+++ b/board/lwmon/flash.c
@@ -112,7 +112,7 @@ unsigned long flash_init (void)
 
        /* Remap FLASH according to real size */
        memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
-                               OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI;
+                               OR_CSNT_SAM | OR_ACS_DIV1;
        memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
 
        DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
@@ -143,7 +143,7 @@ unsigned long flash_init (void)
 
        if (size_b1) {
                memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
-                                       OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI;
+                                       OR_CSNT_SAM | OR_ACS_DIV1;
                memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
                                        BR_PS_32 | BR_V;
 

diff --git a/cpu/mpc824x/drivers/i2c/i2c1.c b/cpu/mpc824x/drivers/i2c/i2c1.c
index 5c627e305a64054c58b1d7196ed7bce9122f9e90..34c88bfe1e3096cd85f1e343950f07979768bbe1 100644 (file)
--- a/cpu/mpc824x/drivers/i2c/i2c1.c
+++ b/cpu/mpc824x/drivers/i2c/i2c1.c
@@ -10,15 +10,15 @@
 #include "i2c_export.h"
 #include "i2c.h"
 
-#undef I2CDBG0
-#define DEBUG
+#undef  I2CDBG0
+#undef  DEBUG
 
 /* Define a macro to use an optional application-layer print function, if
  * one was passed to the I2C library during initialization.  If there was
  * no function pointer passed, this protects against calling it.  Also define
  * the global variable that holds the passed pointer.
  */
-#define TIMEOUT 10*CFG_HZ
+#define TIMEOUT (CFG_HZ/4)
 #define PRINT if ( app_print ) app_print
 static int (*app_print) (char *, ...);
 
@@ -1144,6 +1144,7 @@ int i2c_probe (uchar chip)
         * driver doesn't appear to support sending just the chip address
         * and looking for an <ACK> back.
         */
+       udelay(10000);
        return i2c_read (chip, 0, 1, (char *)&tmp, 1);
 }
 
@@ -1195,6 +1196,9 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
        status = I2C_do_buffer (0, I2C_MASTER_XMIT, chip, alen + len,
                                dummy_buffer, I2C_STOP, 1, I2C_NO_RESTART);
 
+#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
+       udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
        if (status != I2C_SUCCESS) {
                PRINT ("i2c_write: can't perform data transfer\n");
                return 1;

diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S
index 795e40775998ce60648798356438f8f139d8edd7..0d271c0aac25145ffe00c69d47acfe07bde0a3cf 100644 (file)
--- a/cpu/mpc824x/start.S
+++ b/cpu/mpc824x/start.S
@@ -382,6 +382,7 @@ transfer_to_handler:
        lwz     r24,0(r23)              /* virtual address of handler */
        lwz     r23,4(r23)              /* where to go when done */
        mtspr   SRR0,r24
+       ori     r20,r20,0x30            /* enable IR, DR */
        mtspr   SRR1,r20
        mtlr    r23
        SYNC

diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 0aa27f120af80ffc0ed6abf161e28172dc02007b..f807b202109d1ae6863061c73e7df3dba4d5265d 100644 (file)
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -64,6 +64,9 @@
   |  26-Feb-02   stefan.roese@esd-electronics.com
   |              - rx and tx buffer descriptors now allocated (no fixed address
   |                used anymore)
+  |  17-Jun-02   stefan.roese@esd-electronics.com
+  |              - MAL error debug printf 'M' removed (rx de interrupt may
+  |                occur upon many incoming packets with only 4 rx buffers).
   +-----------------------------------------------------------------------------*/
 
 #include <ppcboot.h>
@@ -155,7 +158,7 @@ static int tx_i_index = 0;          /* Transmit Interrupt Queue Index */
 static int tx_u_index = 0;             /* Transmit User Queue Index */
 static int tx_run[NUM_TX_BUFF];        /* Transmit Running Queue */
 
-/* #define INFO_405_ENET 1 */
+#undef INFO_405_ENET 1
 #ifdef INFO_405_ENET
 static int packetSent = 0;
 static int packetReceived = 0;
@@ -611,7 +614,13 @@ void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
        printf ("\nMAL error occured.... ISR = %lx UIC = = %lx  MAL_DEF = %lx  MAL_ERR= %lx \n",
                isr, uic, maldef, mal_errr);
 #else
+#if 0
+       /*
+        * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
+        * many incoming packets with only 4 rx buffers.
+        */
        printf ("M");                   /* just to see something upon mal error */
+#endif
 #endif /*sr */
 
        eth_init (bis_save);            /* start again... */

diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h
index d22df0cbf540874bddaa66e60c5e948205bd1cbd..9f30056b75cd9c08080c0931fdae003a4b3f1863 100644 (file)
--- a/include/config_Sandpoint8240.h
+++ b/include/config_Sandpoint8240.h
@@ -175,6 +175,9 @@
 
 #define CFG_I2C_EEPROM_ADDR    0x57            /* EEPROM IS24C02               */
 #define CFG_I2C_EEPROM_ADDR_LEN        1               /* Bytes of address             */
+#define CFG_EEPROM_PAGE_WRITE_BITS     3       /* write page size              */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10      /* takes up to 10 msec          */
+
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 #define CFG_FLASH_BANKS                { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }