drm/amd/display: Refactor edp ILR caps codes

We split out ILR config from "global" to "per-panel" config settings.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 895c6e6bfeb84390b859a0be863dcee03ba20718..c4daef1e708c96bbd488d4030bca78c399626847 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1307,7 +1307,10 @@ static bool detect_link_and_local_sink(struct dc_link *link,
                }
 
                if (link->connector_signal == SIGNAL_TYPE_EDP) {
-                       // Init dc_panel_config
+                       /* Init dc_panel_config by HW config */
+                       if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
+                               dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
+                       /* Pickup base DM settings */
                        dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
                        // Override dc_panel_config if system has specific settings
                        dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c57df45e83ff56b5c8ef40943962fc45cf008c86..70456580eecc7eba3cf08f27dec2dbd128174695 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5795,7 +5795,7 @@ void detect_edp_sink_caps(struct dc_link *link)
         * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
         */
        if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
-                       (link->dc->debug.optimize_edp_link_rate ||
+                       (link->panel_config.ilr.optimize_edp_link_rate ||
                        link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
                // Read DPCD 00010h - 0001Fh 16 bytes at one shot
                core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
@@ -6744,7 +6744,7 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
        ASSERT(link || crtc_timing); // invalid input
 
        if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
-                       !link->dc->debug.optimize_edp_link_rate)
+                       !link->panel_config.ilr.optimize_edp_link_rate)
                return false;
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2ecf36e6329bd95d26e2ab1c8d9a9ee1454eef38..458a4f431ac6e6adbdafa175fb8a3fe2f0a05b9b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -821,7 +821,6 @@ struct dc_debug_options {
        /* Enable dmub aux for legacy ddc */
        bool enable_dmub_aux_for_legacy_ddc;
        bool disable_fams;
-       bool optimize_edp_link_rate; /* eDP ILR */
        /* FEC/PSR1 sequence enable delay in 100us */
        uint8_t fec_enable_delay_in100us;
        bool enable_driver_sequence_debug;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index bf5f9e2773bc02130a069939d4dc9dddbd0b8428..caf0c7af2d0b9984c5d747d23a7919a2ff55d287 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -138,6 +138,10 @@ struct dc_panel_config {
                bool disable_dsc_edp;
                unsigned int force_dsc_edp_policy;
        } dsc;
+       /* eDP ILR */
+       struct ilr {
+               bool optimize_edp_link_rate; /* eDP ILR */
+       } ilr;
 };
 /*
  * A link contains one or more sinks and their connected status.

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7cb35bb1c0f153608bb3fe47f371807d48029bc5..887081472c0d8e3a0927c51f142e5e48ccf0dc19 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -657,7 +657,6 @@ static const struct dc_debug_options debug_defaults_drv = {
                .usbc_combo_phy_reset_wa = true,
                .dmub_command_table = true,
                .use_max_lb = true,
-               .optimize_edp_link_rate = true
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
@@ -677,6 +676,12 @@ static const struct dc_debug_options debug_defaults_diags = {
                .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+               .ilr = {
+                       .optimize_edp_link_rate = true,
+               },
+};
+
 enum dcn20_clk_src_array_id {
        DCN20_CLK_SRC_PLL0,
        DCN20_CLK_SRC_PLL1,
@@ -1367,6 +1372,11 @@ static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_d
        return &panel_cntl->base;
 }
 
+static void dcn21_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 #define CTX ctx
 
 #define REG(reg_name) \
@@ -1408,6 +1418,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = {
        .set_mcif_arb_params = dcn20_set_mcif_arb_params,
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
        .update_bw_bounding_box = dcn21_update_bw_bounding_box,
+       .get_panel_config_defaults = dcn21_get_panel_config_defaults,
 };
 
 static bool dcn21_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 8745132d6374cff1e5f0dadd07c4b90f2dc96788..fddc21a5a04c4da962648844057592a7d42e01e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -888,7 +888,6 @@ static const struct dc_debug_options debug_defaults_drv = {
                }
        },
        .disable_z10 = true,
-       .optimize_edp_link_rate = true,
        .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
        .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
 };
@@ -911,6 +910,12 @@ static const struct dc_debug_options debug_defaults_diags = {
        .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+       .ilr = {
+               .optimize_edp_link_rate = true,
+       },
+};
+
 static void dcn31_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
@@ -1803,6 +1808,11 @@ validate_out:
        return out;
 }
 
+static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static struct dc_cap_funcs cap_funcs = {
        .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
 };
@@ -1829,6 +1839,7 @@ static struct resource_funcs dcn31_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn31_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .get_panel_config_defaults = dcn31_get_panel_config_defaults,
 };
 
 static struct clock_source *dcn30_clock_source_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 24ec71cbd3e3e536087c1d32d704aff02e97868f..70b647b9b4d3725307ccbc8710802a1b09768fdb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -914,7 +914,6 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .afmt = true,
                }
        },
-       .optimize_edp_link_rate = true,
        .seamless_boot_odm_combine = true
 };
 
@@ -936,6 +935,12 @@ static const struct dc_debug_options debug_defaults_diags = {
        .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+       .ilr = {
+               .optimize_edp_link_rate = true,
+       },
+};
+
 static void dcn31_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
@@ -1675,6 +1680,11 @@ static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
        DC_FP_END();
 }
 
+static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static struct resource_funcs dcn314_res_pool_funcs = {
        .destroy = dcn314_destroy_resource_pool,
        .link_enc_create = dcn31_link_encoder_create,
@@ -1697,6 +1707,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn314_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .get_panel_config_defaults = dcn314_get_panel_config_defaults,
 };
 
 static struct clock_source *dcn30_clock_source_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index eebb42c9ddd605de10481ed00199587d6ba882be..0f71bb86dc9a29fae218ca62109ec2be00f8505d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -885,7 +885,6 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .afmt = true,
                }
        },
-       .optimize_edp_link_rate = true,
        .psr_power_use_phy_fsm = 0,
 };
 
@@ -907,6 +906,12 @@ static const struct dc_debug_options debug_defaults_diags = {
        .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+       .ilr = {
+               .optimize_edp_link_rate = true,
+       },
+};
+
 static void dcn31_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
@@ -1708,6 +1713,11 @@ static int dcn315_populate_dml_pipes_from_context(
        return pipe_cnt;
 }
 
+static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static struct dc_cap_funcs cap_funcs = {
        .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
 };
@@ -1734,6 +1744,7 @@ static struct resource_funcs dcn315_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn315_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .get_panel_config_defaults = dcn315_get_panel_config_defaults,
 };
 
 static bool dcn315_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index f4b52a35ad84fbbf43f31af534ac91933566d25f..6b40a11ac83a92a8085eb64c05ded39f11bab205 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -885,7 +885,6 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .afmt = true,
                }
        },
-       .optimize_edp_link_rate = true,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
@@ -906,6 +905,12 @@ static const struct dc_debug_options debug_defaults_diags = {
        .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+       .ilr = {
+               .optimize_edp_link_rate = true,
+       },
+};
+
 static void dcn31_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
@@ -1710,6 +1715,11 @@ static int dcn316_populate_dml_pipes_from_context(
        return pipe_cnt;
 }
 
+static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static struct dc_cap_funcs cap_funcs = {
        .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
 };
@@ -1736,6 +1746,7 @@ static struct resource_funcs dcn316_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn316_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .get_panel_config_defaults = dcn316_get_panel_config_defaults,
 };
 
 static bool dcn316_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 8919a2092ac508683e44b79f415777a8a1568baa..4ff1392633a7520d2dff743a91473740844b6e03 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -232,6 +232,7 @@ struct resource_funcs {
             unsigned int index);
 
        bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context);
+       void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
 };
 
 struct audio_support{