parent_name = of_clk_get_parent_name(node, 0);
        if (!parent_name) {
                pr_err("%s: missing parent clock\n", __func__);
+               iounmap(reg);
                return;
        }
 
        if (of_property_read_u32(node, "bit-shift", &shift)) {
                pr_err("%s: missing 'shift' property\n", __func__);
+               iounmap(reg);
                return;
        }
 
        if (of_property_read_u32(node, "bit-mask", &mask)) {
                pr_err("%s: missing 'bit-mask' property\n", __func__);
+               iounmap(reg);
                return;
        }
 
        clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
                                 mask, 0, NULL);
-       if (clk)
+       if (clk) {
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
-       else
+       } else {
                pr_err("%s: error registering divider %s\n", __func__, clk_name);
+               iounmap(reg);
+       }
 }
 CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);