return 0;
 }
 
+static void uniphier_spi_handle_err(struct spi_master *master,
+                                   struct spi_message *msg)
+{
+       struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
+       u32 val;
+
+       /* stop running spi transfer */
+       writel(0, priv->base + SSI_CTL);
+
+       /* reset FIFOs */
+       val = SSI_FC_TXFFL | SSI_FC_RXFFL;
+       writel(val, priv->base + SSI_FC);
+
+       uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
+}
+
 static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
 {
        struct uniphier_spi_priv *priv = dev_id;
                                = uniphier_spi_prepare_transfer_hardware;
        master->unprepare_transfer_hardware
                                = uniphier_spi_unprepare_transfer_hardware;
+       master->handle_err = uniphier_spi_handle_err;
        master->num_chipselect = 1;
 
        ret = devm_spi_register_master(&pdev->dev, master);