power-domains = <&dispcc MDSS_GDSC>;
 
                        clocks = <&gcc GCC_DISP_AHB_CLK>,
-                                <&gcc GCC_DISP_AXI_CLK>,
                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
-                       clock-names = "iface", "bus", "core";
+                       clock-names = "iface", "core";
 
                        assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
                        assigned-clock-rates = <300000000>;
                                      <0 0x0aeb0000 0 0x2008>;
                                reg-names = "mdp", "vbif";
 
-                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                               clocks = <&gcc GCC_DISP_AXI_CLK>,
+                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
                                         <&dispcc DISP_CC_MDSS_AXI_CLK>,
                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-                               clock-names = "iface", "bus", "core", "vsync";
+                               clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 
                                assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
                                                  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;