]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
drm/amdgpu: note what type of reset we are using
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 11 Aug 2020 16:02:21 +0000 (12:02 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 14 Aug 2020 21:03:20 +0000 (17:03 -0400)
When we reset the GPU, note what type of reset will be
used.  This makes debugging different reset scenarios
more clear as the driver may use different reset
methods depending on conditions on the system.

Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/vi.c

index c2c67ab68a43b12c5294c3e30231d445babb8f55..7e71ffbca93d8e8ba5ef57f96b4b311c18da6939 100644 (file)
@@ -1366,8 +1366,10 @@ static int cik_asic_reset(struct amdgpu_device *adev)
        int r;
 
        if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+               dev_info(adev->dev, "BACO reset\n");
                r = amdgpu_dpm_baco_reset(adev);
        } else {
+               dev_info(adev->dev, "PCI CONFIG reset\n");
                r = cik_asic_pci_config_reset(adev);
        }
 
index da8024c2826eced6c8097bfb79d2c7ec3a4c2039..54e941e0db608acbc04335941fa00eb20574856a 100644 (file)
@@ -379,7 +379,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
        struct smu_context *smu = &adev->smu;
 
        if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
-               dev_info(adev->dev, "GPU BACO reset\n");
+               dev_info(adev->dev, "BACO reset\n");
 
                ret = smu_baco_enter(smu);
                if (ret)
@@ -387,8 +387,10 @@ static int nv_asic_reset(struct amdgpu_device *adev)
                ret = smu_baco_exit(smu);
                if (ret)
                        return ret;
-       } else
+       } else {
+               dev_info(adev->dev, "MODE1 reset\n");
                ret = nv_asic_mode1_reset(adev);
+       }
 
        return ret;
 }
index e330884edd19649ecad19bbc54d428d0f8554c9d..eaa2f071b139422035ecd6c532e205f444438942 100644 (file)
@@ -1302,6 +1302,8 @@ static int si_asic_reset(struct amdgpu_device *adev)
 {
        int r;
 
+       dev_info(adev->dev, "PCI CONFIG reset\n");
+
        amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
        r = si_gpu_pci_config_reset(adev);
index 84d811b6e48be52204b292a202c7dea92256bd76..3cd98c144bc65d12adf818d626eb0a04fffa8ce7 100644 (file)
@@ -580,10 +580,13 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
 
        switch (soc15_asic_reset_method(adev)) {
                case AMD_RESET_METHOD_BACO:
+                       dev_info(adev->dev, "BACO reset\n");
                        return soc15_asic_baco_reset(adev);
                case AMD_RESET_METHOD_MODE2:
+                       dev_info(adev->dev, "MODE2 reset\n");
                        return amdgpu_dpm_mode2_reset(adev);
                default:
+                       dev_info(adev->dev, "MODE1 reset\n");
                        return soc15_asic_mode1_reset(adev);
        }
 }
index b4e4a7a19d19e459aa6705920e6af544796c2f72..a92880c678410c0225af3057d7efeb0822776963 100644 (file)
@@ -752,8 +752,10 @@ static int vi_asic_reset(struct amdgpu_device *adev)
        int r;
 
        if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+               dev_info(adev->dev, "BACO reset\n");
                r = amdgpu_dpm_baco_reset(adev);
        } else {
+               dev_info(adev->dev, "PCI CONFIG reset\n");
                r = vi_asic_pci_config_reset(adev);
        }