return false;
 }
-
-bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev)
-{
-       struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-       bool exc_err_limit = false;
-
-       if (con && (amdgpu_bad_page_threshold != 0))
-               amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control,
-                                               &exc_err_limit);
-
-       /*
-        * We are only interested in variable exc_err_limit,
-        * as it says if GPU is in bad state or not.
-        */
-       return exc_err_limit;
-}
 
 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
                bool is_ce);
 
-bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev);
-
 /* error handling functions */
 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
                struct eeprom_table_record *bps, int pages);
 
        return curr_address;
 }
 
-int amdgpu_ras_eeprom_check_err_threshold(
-                               struct amdgpu_ras_eeprom_control *control,
-                               bool *exceed_err_limit)
+bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
 {
-       struct amdgpu_device *adev = to_amdgpu_device(control);
-       unsigned char buff[EEPROM_ADDRESS_SIZE +
-                       EEPROM_TABLE_HEADER_SIZE] = { 0 };
-       struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
-       struct i2c_msg msg = {
-                       .addr = control->i2c_address,
-                       .flags = I2C_M_RD,
-                       .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
-                       .buf = buff,
-       };
-       int ret;
-
-       *exceed_err_limit = false;
+       struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 
        if (!__is_ras_eeprom_supported(adev))
-               return 0;
-
-       /* read EEPROM table header */
-       mutex_lock(&control->tbl_mutex);
-       ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
-       if (ret < 1) {
-               dev_err(adev->dev, "Failed to read EEPROM table header.\n");
-               goto err;
-       }
-
-       __decode_table_header_from_buff(hdr, &buff[2]);
+               return false;
 
-       if (hdr->header == EEPROM_TABLE_HDR_BAD) {
+       if (con->eeprom_control.tbl_hdr.header == EEPROM_TABLE_HDR_BAD) {
                dev_warn(adev->dev, "This GPU is in BAD status.");
                dev_warn(adev->dev, "Please retire it or setting one bigger "
                                "threshold value when reloading driver.\n");
-               *exceed_err_limit = true;
+               return true;
        }
 
-err:
-       mutex_unlock(&control->tbl_mutex);
-       return 0;
+       return false;
 }
 
 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 
                        bool *exceed_err_limit);
 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
 
-int amdgpu_ras_eeprom_check_err_threshold(
-                               struct amdgpu_ras_eeprom_control *control,
-                               bool *exceed_err_limit);
+bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
 
 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
                                            struct eeprom_table_record *records,