return 0;
 }
 
-static int
-qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
-{
-       u32 val = 0;
-       val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS);
-       val &= QLA82XX_BOOT_LOADER_MN_ISSUE;
-       if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) {
-               qla_printk(KERN_INFO, ha,
-                       "Memory DIMM SPD not programmed. "
-                       " Assumed valid.\n");
-               return 1;
-       } else if (val) {
-               qla_printk(KERN_INFO, ha,
-                       "Memory DIMM type incorrect.Info:%08X.\n", val);
-               return 2;
-       }
-       return 0;
-}
-
 static int
 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
                u64 off, void *data, int size)
                word[startword+1] |= tmpw >> (sz[0] * 8);
        }
 
-       /*
-        * don't lock here - write_wx gets the lock if each time
-        * write_lock_irqsave(&adapter->adapter_lock, flags);
-        * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
-        */
        for (i = 0; i < loop; i++) {
                temp = off8 + (i << shift_amount);
                qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
        off0[1] = 0;
        sz[1] = size - sz[0];
 
-       /*
-        * don't lock here - write_wx gets the lock if each time
-        * write_lock_irqsave(&adapter->adapter_lock, flags);
-        * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
-        */
-
        for (i = 0; i < loop; i++) {
                temp = off8 + (i << shift_amount);
                qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
                }
        }
 
-       /*
-        * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
-        * write_unlock_irqrestore(&adapter->adapter_lock, flags);
-        */
-
        if (j >= MAX_CTL_CHECK)
                return -1;
 
        qla_printk(KERN_INFO, ha,
            "Cmd Peg initialization failed: 0x%x.\n", val);
 
-       qla82xx_check_for_bad_spd(ha);
        val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
        read_lock(&ha->hw_lock);
        qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);