return 0;
 }
 
+static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
+{
+       int pos;
+       u32 cap, ctrl;
+
+       if (!pci_quirk_intel_spt_pch_acs_match(dev))
+               return -ENOTTY;
+
+       pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
+       if (!pos)
+               return -ENOTTY;
+
+       pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
+       pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
+
+       ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
+
+       pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
+
+       pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
+
+       return 0;
+}
+
 static const struct pci_dev_acs_ops {
        u16 vendor;
        u16 device;
        },
        { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
            .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
+           .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
        },
 };