{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        unsigned long flags;
        bool pending;
 
-       if (i915_reset_in_progress(&dev_priv->gpu_error))
+       if (i915_reset_in_progress(&dev_priv->gpu_error) ||
+           intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
                return false;
 
        spin_lock_irqsave(&dev->event_lock, flags);
        work->enable_stall_check = true;
 
        atomic_inc(&intel_crtc->unpin_work_count);
+       intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
 
        ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
        if (ret)
 
        /* We can share PLLs across outputs if the timings match */
        struct intel_pch_pll *pch_pll;
        uint32_t ddi_pll_sel;
+
+       /* reset counter value when the last flip was submitted */
+       unsigned int reset_counter;
 };
 
 struct intel_plane {