We need set-rate-parent flags for the display's clock path so that the
DSS driver can change the clock rate of the PLL.
This patchs adds the ti,set-rate-parent flag to disp_clk and
dpll_disp_m2_ck clock nodes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
                reg = <0x2e30>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_per_ck: dpll_per_ck {
                compatible = "ti,mux-clock";
                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
                reg = <0x4244>;
+               ti,set-rate-parent;
        };
 
        dpll_extdev_ck: dpll_extdev_ck {