MIPS: inst.h: Add new MIPS R6 FPU opcodes

Add opcodes for the new MIPS R6 FPU instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10952/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 3dce80e679488d42623a874852ee18faaa7fcd83..9b44d5a816fa3ee64faf18a80c7f415dfb681a4d 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -167,8 +167,13 @@ enum cop1_sdw_func {
        fround_op    =  0x0c, ftrunc_op    =  0x0d,
        fceil_op     =  0x0e, ffloor_op    =  0x0f,
        fmovc_op     =  0x11, fmovz_op     =  0x12,
-       fmovn_op     =  0x13, frecip_op    =  0x15,
-       frsqrt_op    =  0x16, fcvts_op     =  0x20,
+       fmovn_op     =  0x13, fseleqz_op   =  0x14,
+       frecip_op    =  0x15, frsqrt_op    =  0x16,
+       fselnez_op   =  0x17, fmaddf_op    =  0x18,
+       fmsubf_op    =  0x19, frint_op     =  0x1a,
+       fclass_op    =  0x1b, fmin_op      =  0x1c,
+       fmina_op     =  0x1d, fmax_op      =  0x1e,
+       fmaxa_op     =  0x1f, fcvts_op     =  0x20,
        fcvtd_op     =  0x21, fcvte_op     =  0x22,
        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
        fcmp_op      =  0x30