Currently OMAP2+ devices are using the function __omap_dm_timer_reset() to
configure the clock-activity, idle, wakeup-enable and auto-idle fields in the
timer OCP_CFG register. The name of the function is mis-leading because this
function does not actually perform a reset of the timer.
For OMAP2+ devices, HWMOD is responsible for reseting and configuring the
timer OCP_CFG register. Therefore, do not use __omap_dm_timer_reset() for
OMAP2+ devices and rely on HWMOD. Furthermore, some timer instances do not
have the fields clock-activity, wakeup-enable and auto-idle and so this
function could configure the OCP_CFG register incorrectly.
Currently HWMOD is not configuring the clock-activity field in the OCP_CFG
register for timers that have this field. Commit 
0f0d080 (ARM: OMAP: DMTimer:
Use posted mode) configures the clock-activity field to keep the f-clk enabled
so that the wake-up capability is enabled. Therefore, add the appropriate flags
to the timer HWMOD structures to configure this field in the same way.
For OMAP2/3 devices all dmtimers have the clock-activity field, where as for
OMAP4 devices, only dmtimer 1, 2 and 10 have the clock-activity field.
Verified on OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda that HWMOD is
configuring the dmtimer OCP_CFG register as expected for clock-events timer.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
 
                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+       .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
        },
        .dev_attr       = &capability_alwon_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer2 */
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer3 */
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer4 */
                },
        },
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer5 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer6 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer7 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer8 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer9 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer10 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer11 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer12 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap2xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* wd_timer2 */
 
                           SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
                           SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+       .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
        },
        .dev_attr       = &capability_alwon_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer2 */
                },
        },
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer3 */
                },
        },
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer4 */
                },
        },
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer5 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer6 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer7 */
        },
        .dev_attr       = &capability_dsp_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer8 */
        },
        .dev_attr       = &capability_dsp_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer9 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer10 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer11 */
        },
        .dev_attr       = &capability_pwm_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /* timer12 */
        },
        .dev_attr       = &capability_secure_dev_attr,
        .class          = &omap3xxx_timer_hwmod_class,
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 /*
 
                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
                           SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+       .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
        .name           = "timer1",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_wkup_clkdm",
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer1_irqs,
        .main_clk       = "timer1_fck",
        .prcm = {
        .name           = "timer2",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer2_irqs,
        .main_clk       = "timer2_fck",
        .prcm = {
        .name           = "timer10",
        .class          = &omap44xx_timer_1ms_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
+       .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_timer10_irqs,
        .main_clk       = "timer10_fck",
        .prcm = {
 
                }
        }
        __omap_dm_timer_init_regs(timer);
-       __omap_dm_timer_reset(timer, 1, 1);
 
        if (posted)
                __omap_dm_timer_enable_posted(timer);