dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller

Document bindings for the T-Head TH1520 AP sub-system clock controller.

Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Co-developed-by: Yangtao Li <frank.li@vivo.com>
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/r/20240623-th1520-clk-v2-1-ad8d6432d9fb@tenstorrent.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
new file mode 100644 (file)
index 0000000..0129bd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD TH1520 AP sub-system clock controller
+
+description: |
+  The T-HEAD TH1520 AP sub-system clock controller configures the
+  CPU, DPU, GMAC and TEE PLLs.
+
+  SoC reference manual
+  https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+  - Wei Fu <wefu@redhat.com>
+  - Drew Fustini <dfustini@tenstorrent.com>
+
+properties:
+  compatible:
+    const: thead,th1520-clk-ap
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: main oscillator (24MHz)
+
+  "#clock-cells":
+    const: 1
+    description:
+      See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/thead,th1520-clk-ap.h>
+    clock-controller@ef010000 {
+        compatible = "thead,th1520-clk-ap";
+        reg = <0xef010000 0x1000>;
+        clocks = <&osc>;
+        #clock-cells = <1>;
+    };

diff --git a/MAINTAINERS b/MAINTAINERS
index d6c90161c7bfe3886e675396cb2d2d7b44acc3b3..04eb5587ffa73df840e08141d67d5763c042a5ff 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19322,7 +19322,9 @@ M:      Guo Ren <guoren@kernel.org>
 M:     Fu Wei <wefu@redhat.com>
 L:     linux-riscv@lists.infradead.org
 S:     Maintained
+F:     Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
 F:     arch/riscv/boot/dts/thead/
+F:     include/dt-bindings/clock/thead,th1520-clk-ap.h
 
 RNBD BLOCK DRIVERS
 M:     Md. Haris Iqbal <haris.iqbal@ionos.com>

diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h
new file mode 100644 (file)
index 0000000..a199784
--- /dev/null
+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
+ * Authors: Yangtao Li <frank.li@vivo.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_TH1520_H_
+#define _DT_BINDINGS_CLK_TH1520_H_
+
+#define CLK_CPU_PLL0           0
+#define CLK_CPU_PLL1           1
+#define CLK_GMAC_PLL           2
+#define CLK_VIDEO_PLL          3
+#define CLK_DPU0_PLL           4
+#define CLK_DPU1_PLL           5
+#define CLK_TEE_PLL            6
+#define CLK_C910_I0            7
+#define CLK_C910               8
+#define CLK_BROM               9
+#define CLK_BMU                        10
+#define CLK_AHB2_CPUSYS_HCLK   11
+#define CLK_APB3_CPUSYS_PCLK   12
+#define CLK_AXI4_CPUSYS2_ACLK  13
+#define CLK_AON2CPU_A2X                14
+#define CLK_X2X_CPUSYS         15
+#define CLK_AXI_ACLK           16
+#define CLK_CPU2AON_X2H                17
+#define CLK_PERI_AHB_HCLK      18
+#define CLK_CPU2PERI_X2H       19
+#define CLK_PERI_APB_PCLK      20
+#define CLK_PERI2APB_PCLK      21
+#define CLK_PERISYS_APB1_HCLK  22
+#define CLK_PERISYS_APB2_HCLK  23
+#define CLK_PERISYS_APB3_HCLK  24
+#define CLK_PERISYS_APB4_HCLK  25
+#define CLK_OSC12M             26
+#define CLK_OUT1               27
+#define CLK_OUT2               28
+#define CLK_OUT3               29
+#define CLK_OUT4               30
+#define CLK_APB_PCLK           31
+#define CLK_NPU                        32
+#define CLK_NPU_AXI            33
+#define CLK_VI                 34
+#define CLK_VI_AHB             35
+#define CLK_VO_AXI             36
+#define CLK_VP_APB             37
+#define CLK_VP_AXI             38
+#define CLK_CPU2VP             39
+#define CLK_VENC               40
+#define CLK_DPU0               41
+#define CLK_DPU1               42
+#define CLK_EMMC_SDIO          43
+#define CLK_GMAC1              44
+#define CLK_PADCTRL1           45
+#define CLK_DSMART             46
+#define CLK_PADCTRL0           47
+#define CLK_GMAC_AXI           48
+#define CLK_GPIO3              49
+#define CLK_GMAC0              50
+#define CLK_PWM                        51
+#define CLK_QSPI0              52
+#define CLK_QSPI1              53
+#define CLK_SPI                        54
+#define CLK_UART0_PCLK         55
+#define CLK_UART1_PCLK         56
+#define CLK_UART2_PCLK         57
+#define CLK_UART3_PCLK         58
+#define CLK_UART4_PCLK         59
+#define CLK_UART5_PCLK         60
+#define CLK_GPIO0              61
+#define CLK_GPIO1              62
+#define CLK_GPIO2              63
+#define CLK_I2C0               64
+#define CLK_I2C1               65
+#define CLK_I2C2               66
+#define CLK_I2C3               67
+#define CLK_I2C4               68
+#define CLK_I2C5               69
+#define CLK_SPINLOCK           70
+#define CLK_DMA                        71
+#define CLK_MBOX0              72
+#define CLK_MBOX1              73
+#define CLK_MBOX2              74
+#define CLK_MBOX3              75
+#define CLK_WDT0               76
+#define CLK_WDT1               77
+#define CLK_TIMER0             78
+#define CLK_TIMER1             79
+#define CLK_SRAM0              80
+#define CLK_SRAM1              81
+#define CLK_SRAM2              82
+#define CLK_SRAM3              83
+#define CLK_PLL_GMAC_100M      84
+#define CLK_UART_SCLK          85
+#endif