drm/msm/a5xx: Always set an OPP supported hardware value

[ Upstream commit 0478b4fc5f37f4d494245fe7bcce3f531cf380e9 ]

If the opp table specifies opp-supported-hw as a property but the driver
has not set a supported hardware value the OPP subsystem will reject
all the table entries.

Set a "default" value that will match the default table entries but not
conflict with any possible real bin values. Also fix a small memory leak
and free the buffer allocated by nvmem_cell_read().

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 1fc9a7fa37b459d6870d68a7f602d06d6c8073ae..d29a58bd2f7a363f65e1b76a615cf026ef9e63d6 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1474,18 +1474,31 @@ static const struct adreno_gpu_funcs funcs = {
 static void check_speed_bin(struct device *dev)
 {
        struct nvmem_cell *cell;
-       u32 bin, val;
+       u32 val;
+
+       /*
+        * If the OPP table specifies a opp-supported-hw property then we have
+        * to set something with dev_pm_opp_set_supported_hw() or the table
+        * doesn't get populated so pick an arbitrary value that should
+        * ensure the default frequencies are selected but not conflict with any
+        * actual bins
+        */
+       val = 0x80;
 
        cell = nvmem_cell_get(dev, "speed_bin");
 
-       /* If a nvmem cell isn't defined, nothing to do */
-       if (IS_ERR(cell))
-               return;
+       if (!IS_ERR(cell)) {
+               void *buf = nvmem_cell_read(cell, NULL);
+
+               if (!IS_ERR(buf)) {
+                       u8 bin = *((u8 *) buf);
 
-       bin = *((u32 *) nvmem_cell_read(cell, NULL));
-       nvmem_cell_put(cell);
+                       val = (1 << bin);
+                       kfree(buf);
+               }
 
-       val = (1 << bin);
+               nvmem_cell_put(cell);
+       }
 
        dev_pm_opp_set_supported_hw(dev, &val, 1);
 }