mutex_unlock(&dev_priv->dpll_lock);
 }
 
+static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
+{
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+       u32 tmp;
+       enum port port;
+
+       mutex_lock(&dev_priv->dpll_lock);
+       tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+       for_each_dsi_port(port, intel_dsi->ports) {
+               tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+       }
+
+       I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+       mutex_unlock(&dev_priv->dpll_lock);
+}
+
 static void
 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
                               const struct intel_crtc_state *pipe_config)
        u32 tmp;
        enum port port;
 
+       gen11_dsi_ungate_clocks(encoder);
        for_each_dsi_port(port, intel_dsi->ports) {
                tmp = I915_READ(DDI_BUF_CTL(port));
                tmp &= ~DDI_BUF_CTL_ENABLE;
                        DRM_ERROR("DDI port:%c buffer not idle\n",
                                  port_name(port));
        }
+       gen11_dsi_ungate_clocks(encoder);
 }
 
 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)