arm64: dts: ti: k3-j722s-main: Switch to 64-bit address space for PCIe0

The PCIe0 instance of PCIe in J722S SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250422120042.3746004-7-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 562dfbdf449d096620853ffc0f642526f2a070f4..78d7e800b311549848097a8febab63d0851be57b 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -98,10 +98,10 @@
                reg = <0x00 0x0f102000 0x00 0x1000>,
                      <0x00 0x0f100000 0x00 0x400>,
                      <0x00 0x0d000000 0x00 0x00800000>,
-                     <0x00 0x68000000 0x00 0x00001000>;
+                     <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
                reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-               ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
-                        <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+               ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+                        <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
                dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
                interrupt-names = "link_state";
                interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;