interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
+       thermal@e61f0000 {
+               compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
+               reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+               interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
+               power-domains = <&cpg_clocks>;
+       };
+
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
                        clock-indices = <R8A7793_CLK_IRQC>;
                        clock-output-names = "irqc";
                };
+               mstp5_clks: mstp5_clks@e6150144 {
+                       compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                       clocks = <&extal_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <R8A7793_CLK_THERMAL>;
+                       clock-output-names = "thermal";
+               };
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7793-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";