Revert "drm/amd/display: Fix VUpdate offset calculations for dcn401"

This reverts commit fe45e2af4a22e569b35b7f45eb9f040f6fbef94f.

Reason for revert: it causes stuttering in some usecases.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 79f4eaf8fc5202ab90a2a023ee07746928c46ee2..5489f3d431f64d97523ba194739980e3fdf1251d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -2646,47 +2646,3 @@ void dcn401_plane_atomic_power_down(struct dc *dc,
        if (hws->funcs.dpp_root_clock_control)
                hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
 }
-
-/*
- * apply_front_porch_workaround
- *
- * This is a workaround for a bug that has existed since R5xx and has not been
- * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
- */
-static void apply_front_porch_workaround(
-       struct dc_crtc_timing *timing)
-{
-       if (timing->flags.INTERLACE == 1) {
-               if (timing->v_front_porch < 2)
-                       timing->v_front_porch = 2;
-       } else {
-               if (timing->v_front_porch < 1)
-                       timing->v_front_porch = 1;
-       }
-}
-
-int dcn401_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
-{
-       const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
-       struct dc_crtc_timing patched_crtc_timing;
-       int vesa_sync_start;
-       int asic_blank_end;
-       int interlace_factor;
-
-       patched_crtc_timing = *dc_crtc_timing;
-       apply_front_porch_workaround(&patched_crtc_timing);
-
-       interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
-
-       vesa_sync_start = patched_crtc_timing.v_addressable +
-                       patched_crtc_timing.v_border_bottom +
-                       patched_crtc_timing.v_front_porch;
-
-       asic_blank_end = (patched_crtc_timing.v_total -
-                       vesa_sync_start -
-                       patched_crtc_timing.v_border_top)
-                       * interlace_factor;
-
-       return asic_blank_end -
-                       pipe_ctx->global_sync.dcn4x.vstartup_lines + 1;
-}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index 37c915568afcbc785234af56d1464ee9f1b65d43..781cf0efccc6cdf395c971fade567691242623ac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -109,5 +109,4 @@ void dcn401_detect_pipe_changes(
 void dcn401_plane_atomic_power_down(struct dc *dc,
                struct dpp *dpp,
                struct hubp *hubp);
-int dcn401_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
 #endif /* __DC_HWSS_DCN401_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index aa9573ce44fce76885053923f72b3de4e49450a3..fe7aceb2f5104a94938db1f8e9b8c121c24a2868 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -73,7 +73,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
        .init_sys_ctx = dcn20_init_sys_ctx,
        .init_vm_ctx = dcn20_init_vm_ctx,
        .set_flip_control_gsl = dcn20_set_flip_control_gsl,
-       .get_vupdate_offset_from_vsync = dcn401_get_vupdate_offset_from_vsync,
+       .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
        .calc_vupdate_position = dcn10_calc_vupdate_position,
        .apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations,
        .does_plane_fit_in_mall = NULL,