#define CDC_VA_FS_CONTROL_EN                   BIT(0)
 #define CDC_VA_FS_COUNTER_CLR                  BIT(1)
 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL                (0x0008)
+#define CDC_VA_SWR_RESET_MASK          BIT(1)
+#define CDC_VA_SWR_RESET_ENABLE                BIT(1)
+#define CDC_VA_SWR_CLK_EN_MASK         BIT(0)
+#define CDC_VA_SWR_CLK_ENABLE          BIT(0)
 #define CDC_VA_TOP_CSR_TOP_CFG0                        (0x0080)
 #define CDC_VA_FS_BROADCAST_EN                 BIT(1)
 #define CDC_VA_TOP_CSR_DMIC0_CTL               (0x0084)
 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0            (0x00D0)
 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1            (0x00D4)
 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2            (0x00D8)
+#define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK                (0xEE)
+#define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1                (0xCC)
 #define CDC_VA_TOP_CSR_SWR_CTRL                        (0x00DC)
 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0           (0x0100)
 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1           (0x0104)
        unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
        unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
        u16 dmic_clk_div;
+       bool has_swr_master;
 
        int dec_mode[VA_MACRO_NUM_DECIMATORS];
        struct regmap *regmap;
 
 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
 
+struct va_macro_data {
+       bool has_swr_master;
+};
+
+static const struct va_macro_data sm8250_va_data = {
+       .has_swr_master = false,
+};
+
+static const struct va_macro_data sm8450_va_data = {
+       .has_swr_master = true,
+};
+
 static bool va_is_volatile_register(struct device *dev, unsigned int reg)
 {
        switch (reg) {
        case CDC_VA_TOP_CSR_DMIC2_CTL:
        case CDC_VA_TOP_CSR_DMIC3_CTL:
        case CDC_VA_TOP_CSR_DMIC_CFG:
+       case CDC_VA_TOP_CSR_SWR_MIC_CTL0:
+       case CDC_VA_TOP_CSR_SWR_MIC_CTL1:
+       case CDC_VA_TOP_CSR_SWR_MIC_CTL2:
        case CDC_VA_TOP_CSR_DEBUG_BUS:
        case CDC_VA_TOP_CSR_DEBUG_EN:
        case CDC_VA_TOP_CSR_TX_I2S_CTL:
 
 static int fsgen_gate_enable(struct clk_hw *hw)
 {
-       return va_macro_mclk_enable(to_va_macro(hw), true);
+       struct va_macro *va = to_va_macro(hw);
+       struct regmap *regmap = va->regmap;
+       int ret;
+
+       ret = va_macro_mclk_enable(va, true);
+       if (!va->has_swr_master)
+               return ret;
+
+       regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
+                          CDC_VA_SWR_RESET_MASK,  CDC_VA_SWR_RESET_ENABLE);
+
+       regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
+                          CDC_VA_SWR_CLK_EN_MASK,
+                          CDC_VA_SWR_CLK_ENABLE);
+       regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
+                          CDC_VA_SWR_RESET_MASK, 0x0);
+
+       return ret;
 }
 
 static void fsgen_gate_disable(struct clk_hw *hw)
 {
-       va_macro_mclk_enable(to_va_macro(hw), false);
+       struct va_macro *va = to_va_macro(hw);
+       struct regmap *regmap = va->regmap;
+
+       if (va->has_swr_master)
+               regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
+                          CDC_VA_SWR_CLK_EN_MASK, 0x0);
+
+       va_macro_mclk_enable(va, false);
 }
 
 static int fsgen_gate_is_enabled(struct clk_hw *hw)
 static int va_macro_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
+       const struct va_macro_data *data;
        struct va_macro *va;
        void __iomem *base;
        u32 sample_rate = 0;
 
        dev_set_drvdata(dev, va);
 
+       data = of_device_get_match_data(dev);
+       va->has_swr_master = data->has_swr_master;
+
        /* mclk rate */
        clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
 
                goto err_clkout;
        }
 
+       if (va->has_swr_master) {
+               /* Set default CLK div to 1 */
+               regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
+               regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
+               regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
+                                 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
+
+       }
+
        ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
                                              va_macro_dais,
                                              ARRAY_SIZE(va_macro_dais));
 };
 
 static const struct of_device_id va_macro_dt_match[] = {
-       { .compatible = "qcom,sc7280-lpass-va-macro" },
-       { .compatible = "qcom,sm8250-lpass-va-macro" },
+       { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
+       { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
+       { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
+       { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
        {}
 };
 MODULE_DEVICE_TABLE(of, va_macro_dt_match);