enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        u32 chicken;
 
-       if (!HAS_PSR(dev_priv)) {
-               DRM_DEBUG_KMS("PSR not supported on this platform\n");
+       if (!HAS_PSR(dev_priv))
                return;
-       }
 
        if (!is_edp_psr(intel_dp)) {
                DRM_DEBUG_KMS("PSR not supported by this panel\n");
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
 
+       if (!HAS_PSR(dev_priv))
+               return;
+
        mutex_lock(&dev_priv->psr.lock);
        if (!dev_priv->psr.enabled) {
                mutex_unlock(&dev_priv->psr.lock);
        enum pipe pipe;
        u32 val;
 
+       if (!HAS_PSR(dev_priv))
+               return;
+
        /*
         * Single frame update is already supported on BDW+ but it requires
         * many W/A and it isn't really needed.
        struct drm_crtc *crtc;
        enum pipe pipe;
 
+       if (!HAS_PSR(dev_priv))
+               return;
+
        mutex_lock(&dev_priv->psr.lock);
        if (!dev_priv->psr.enabled) {
                mutex_unlock(&dev_priv->psr.lock);
        struct drm_crtc *crtc;
        enum pipe pipe;
 
+       if (!HAS_PSR(dev_priv))
+               return;
+
        mutex_lock(&dev_priv->psr.lock);
        if (!dev_priv->psr.enabled) {
                mutex_unlock(&dev_priv->psr.lock);
  */
 void intel_psr_init(struct drm_i915_private *dev_priv)
 {
+       if (!HAS_PSR(dev_priv))
+               return;
+
        dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
                HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;